Posted on June 15, 2007 at 00:22what may be wrong between Jlink and IAR workbench with message below?
Fri Jun 15 09:19:16 2007: J-Link firmware: V1.20 (J-Link compiled Feb 08 2006 15:44:22 ARM Rev.5)
Fri Jun 15 09:19:16 2007: JTAG speed is initially set to: 4000 kHz
Fri Jun 15 09:19:16 2007: Resetting Target using RESET pin
Fri Jun 15 09:19:16 2007: Halting CPU core
Fri Jun 15 09:19:16 2007: Initial reset was performed
Fri Jun 15 09:19:16 2007: J-Link found 1 JTAG device. ARM core Id: 3F0F0F0F(ARM7)
Fri Jun 15 09:19:16 2007: Device at TAP0 selected
Fri Jun 15 09:19:16 2007: **** Warning: Chip has already been halted.
Fri Jun 15 09:19:16 2007: Auto JTAG speed: 4000 kHz
Fri Jun 15 09:19:17 2007: 4545 bytes downloaded (8.11 Kbytes/sec)
Fri Jun 15 09:19:17 2007: Loaded debugee: C:\Program Files\IAR Systems\Embedded Workbench 4.0 Kickstart\arm\
config\flashloader\ST\FlashSTR71xF.d79
Fri Jun 15 09:19:17 2007: Target reset
Fri Jun 15 09:19:36 2007: Memory access timed out @ 20000B5C
Fri Jun 15 09:19:55 2007: Code still contains old breakpoints
