STR910 Instruction and GPIO speed

m_j_butcher · ‎2008-10-08

Posted on October 09, 2008 at 05:33

m_j_butcher · ‎2011-05-17

Posted on May 17, 2011 at 09:35

Hi Mark 2

I have been communicating with a couple of others who are experimenting.

Presently the situation is that 6MHz toggle rate is the best that probably can be achieved (the 12M specified in ST presentations seems to really mean that an edge can be generated at 12M rate, resulting in 6MHz square wave).

Two other pieces of info are important:

96 MHz is max for CPU and 48 MHz is max for APB (PCM = MCLK/2). Above 75M the flash needs 2 wait states which is programmed using the FMI configuration command (see the FLASH users manual and not the device data sheet).

(I didn't actually manage to get this working on a first attempt but maybe because a clock was still out of spec. some where)

It also seems that various clocking strategies/buffering modes are better for certain jobs and so it depends a bit on what is being optimised for. One piece of info that I received is interesting - it may be a good strategy to clock at 73MHz so that no dividers are used and no extra wait states are needed (not exactly sure where 73MHz comes from - perhaps experimental?) and the overall performance may then be best.

I haven't actually been able to do any more detailed work because the software application was getting way behind schedule - with the 20MIPs I can limp by for the moment. Once there is breathing space I will try to sort out the PLL rate which should be adequate for the present work.

Please tell if you have something more.

Regards

Mark

mark9 · ‎2011-05-17

Posted on May 17, 2011 at 09:35

Here is my empirical formula for the fastest speed in switching a GPIO, (assuming the code, flash, APB buffer are optimized and turned on).

time = 4/MCLK + 2/PCLK

For example, MCLK=96MHz, PCLK=48MHz, time = 83.33 ns (which is the minimum time)

Here are the required statements to get optimized core performance:

in 91x_init.s, uncomment this line:

#define BUFFERED_Mode ; Work on Buffered mode, when enabling this

in your main app,

// This example toggles LED9, P6.0, on the IAR demo board STR912-SK

FMI_Config(FMI_READ_WAIT_STATE_2,FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,

FMI_LVD_ENABLE,FMI_FREQ_HIGH);

if (ERROR == SCU_PLLFactorsConfig(192,25,3)) {

while(1);

}

if (ERROR == SCU_PLLCmd(ENABLE)) { // also waits for PLL to lock.

while(1);

}

SCU_PCLKDivisorConfig(SCU_PCLK_Div2);

if (ERROR == SCU_MCLKSourceConfig(SCU_MCLK_PLL)) {

while(1);

}

SCU_PFQBCCmd(ENABLE); // enable branch cache

GPIO_InitTypeDef GPIO_InitStructure;

SCU_APBPeriphClockConfig(__GPIO6, ENABLE);

GPIO_StructInit(&GPIO_InitStructure);

GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2;

GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt1 ;

GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;

GPIO_Init (GPIO6, &GPIO_InitStructure);

while (1) {

*(U32*)(0x4800C004) = 0x00000000;

*(U32*)(0x4800C004) = 0x00000001;

*(U32*)(0x4800C004) = 0x00000000;

*(U32*)(0x4800C004) = 0x00000001;

}

mark9 · ‎2011-05-17

Posted on May 17, 2011 at 09:35

This is wild speculation on my part, since I know little about chip clocking. But assuming that writes to the AHB/APB are interlocked and not pipelineable, then the following clocks would explain what we see

3 MCLK clocks to write to the AHB (ARM9 core speed of STR instruction)

1 MCLK clock to transfer AHB to APB

2 PCLK clocks to transfer APB to GPIO pin

The first 2 types run at MCLK=RCLK, the latter runs at PCLK=MCLK or MCLK/2. If you do the math:

a 48 MHz PLL, 48MHz PCLK will give 120 ns per edge.

a 96 MHz PLL, 48MHz PCLK will give 80 ns per edge.

I think the bottom line is for high frequency applications, GPIO bit banging is not the way to go, but it is a useful exercise to understand where the cycles are going.

The good news is that the CORE has spare cycles to do other things while it is waiting for the GPIO. I was able to stick in a lot of NOPs into my loop and not change the GPIO-toggling throughput at all. So good scheduling will help.

Someone that understands uP architecture better is invited to correct and enlighten me! please!

electrogvlieghe · ‎2011-05-17

Posted on May 17, 2011 at 09:35

Hello,

I develop an application with the STR9-Comstick. The idea is to control the I/O ports with a program in Visual Basic through the USB-B connector near the pins of I/O ports.

Which dll use for that for the enumeration ?

The first application will be to generate a TTL signal for differents frequencies through a pin of the I/O ports. Is there a way to program it in C (TTL signal) for the STR9 ? And so the program in VB ?

Thanks

dorrachendoul · ‎2013-04-03

Posted on April 03, 2013 at 14:57

Hello,

Where can i find STM3240G-eval examples.

Thank you