Posted on April 19, 2007 at 13:11Jonn,
Some ramblimg thoughts/alternate methods...
All this comes from thinking about your postings ( this one and previous )and reading the f29 datasheet. I have only worked with the 2264 and not the flite series...
For RX of data:
At program init load the ATR with a large value ( 4091 ). This will be loaded into the CNTR every CNTR overflow which in this case will happen every 5 CNTR clocks. Keep the number close to the ATR maximum to reduce timing offset error.
When the start bit transition is received load the ATR with a value equal to one-half of the bit time you want to receive ( This value is determined by the clock source applied to CNTR and the baud rate you are trying to receive. The one-half value will place the next OVF interrupt at the middle of the start bit for sampling it for correctness. ) and enable the CNTR OVF interrupt. The CNTR is somewhere in a cycle between 4091 and overflow. When CNTR overflows ( within 5 CNTR clocks ) it will be reloaded with the one-half bit time and the OVF interrupt will be asserted ( here is where keeping the initial ATR value large reduces the timing error as the next OVF interrupt will happen a number of CNTR clocks later whose value is the sum of the remainder of the CNTR cycle of (4091 to overflow cycle) + the one half bit time value. ). Service the interrupt by setting the ATR to a full bit time value and re-enable the OVF interrupt. Also sample the input bit ( start bit ) to check it is still low and thus a valid start bit.
The next OVF interrupt will occur midway of the first data bit. Service the interrupt by re-enabling the OVF interrupt. Sample the input bit for its value. Also the CNTR will reload with a full bit time count value.
The next OVF interrupt will occur midway in the second data bit. etc....
Repeat this until the stop bit is received. At that time set the ATR back to 4091 to begin the short CNTR to overflow cycling awaiting the next byte. Leave the OVF interrupt off during this idling period.
Transmitting data could use a similar scheme just use the full bit time count value and set the output pin to the desired bit state each OVF interrupt.
The above method limits you to TX only or RX only at any given time ( half-duplex ). I don't think you do full-duplex comms with this scheme.
Another possibility....
Maybe you could use a PWM channel to make a full-duplex capability. Set the pwm frequency to the full bit time you want to use and set the DCRxH/DCRxL to the half bit time. Connect the pwm output pin to another pin configured as input/interrupt. On CNTR overflow/pwm cycle restart/pwm output pin transition do the transmit function so there is a full bit time between bit transitions and use the DCRx count point to do the receive so that would put that transition in the middle of the receive bit time. Haven't thought about this one much.
pjr
