2024-10-20 02:19 AM
I would like to determine MCU's behavior when two simultaneous events trigger interrupts on a single timer. For instance on TIM2, if both the output compare register and auto-reload register hold the same value and both corresponding interrupts are enabled, is a single interrupt generated or are interrupts generated for each event? In the STM32 HAL (stm32f1xx_hal_tim.c) a single ISR (void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)) is called for all interrupts generated by the timer events. The ISR essentially prioritizes interrupts through a sequence of if/else instructions. I think if two interrupts are generated, a callback for the high-priority would be generated while the other interrupt would be pending. Otherwise, only the higher priority interrupt would be recognized. I did RFTM but did not find the answer to this.
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2024-10-20 11:19 PM - edited 2024-10-20 11:19 PM
Timer interrupt is triggered if any of timer event flags for events unmasked in DIER register is set. It remains triggered until all the unmasked event flags are cleared. The flags are cleared by software, so the interrupt will stay active until your ISR clears all flags causing the interrupt.
2024-10-20 02:25 AM
Yes, in STM32F1xx there is only one single interrupt for all TIM2 interrupts.
> The ISR essentially prioritizes interrupts through a sequence of if/else instructions.
Yes, but you are not obliged to use the Cube/HAL ISR. Write your own, if this does not suit your application; in that you can prioritize the individual interrupts in the way you need.
JW
2024-10-20 08:40 PM
Thanks for the response. Do you know whether simultaneous events create a single of two interrupts? Your suggestion about writing my own ISR is what I have in mind if it is needed.
2024-10-20 11:19 PM - edited 2024-10-20 11:19 PM
Timer interrupt is triggered if any of timer event flags for events unmasked in DIER register is set. It remains triggered until all the unmasked event flags are cleared. The flags are cleared by software, so the interrupt will stay active until your ISR clears all flags causing the interrupt.
2024-10-20 11:40 PM
One. All interrupt sources are ORed and the interrupt is level sensitive.
JW
2024-10-21 01:04 AM
Your (and waclawek.jan) explanation along with a couple of experiments cleared everything up for me. Thanks for the responses.