STR750 UART TX FIFO Interrupts

[jpeacock2]

Posted on August 30, 2007 at 19:26

STR750 UART TX FIFO Interrupts

[jpeacock2]

Posted on August 29, 2007 at 17:14

On the STR750 the reference manual says a TRANSMIT interrupt occurs when the UART TX FIFO reaches the preset watermark (8 bytes in this case). But the manual isn't clear if the interrupt is a level (always asserted if below 8 bytes) or an edge (transition from 9 to 8 bytes) fed to the EIC interrupt controller. Are there any examples of UART TX interrupts with FIFOs enabled? Do I have to disable the TRANSMIT interrupt if the FIFO falls below the watermark?

Environment is a custom STR750 board, Eclipse 3.2, GCC 4.2 and OpenOCD. Jack (last name censored by forum software, but it's a large african bird starting with ''Pea'', famed for the tail)

[kaouther]

Posted on August 30, 2007 at 13:08

Dear,

An example of UART TX interrupts using FIFO is available in STR75x standard library '' Example 2'' configuring the transmit FIFO level and UART Transmit interrupt. Regards.

[jpeacock2]

Posted on August 30, 2007 at 15:31

Unfortunately the ST examples are contrived to avoid many of the programming questions with FIFOs. I looked at the library examples but all of them use fixed tansfer sizes which avoid FIFO full/watermark/empty issues, and none of the examples are set up for continuous data transfers, such as sending variable size strings with interrupts.

The examples disable interrupts after a fixed transfer (always less than the FIFO size), which does not answer the original question...is the UARTx_IT_Transmit interrupt continuously asserted when the TX FIFO drops below the watermark, or is it a single event triggered by passing through the watermark count?

[jpeacock2]

Posted on August 30, 2007 at 19:26

After some trial and error, looks like UART interrupts are edge triggered. A transmit interrupt occurs at the point the TX FIFO drops below the watermark, but is not asserted continually after that point.

Which begs the question, why are interrupts disabled in the ST library examples at the end of a transfer? I interpreted this as blocking some continuous IRQ request, but that's not the case. Not at all obvious why the disable is needed.