Posted on May 17, 2011 at 13:23Are you sure your receiver is triggering on the right clock edge? SPI can be set up to receive data on rising or falling edge. And does your receiver match clock idle (normally hi, or normally low)? Do you run the sign...
Posted on May 17, 2011 at 13:10What you might consider is buffering the data in RAM in the slave processor. Use a GPIO pin from the master to generate an interrupt on the slave, indicating the master is ready to receive data. The slave then sets up ...
Posted on May 17, 2011 at 13:10I've seen this behavior on I2C with certain periphal chips that don't always reset to a clean state, or hang during a bus transaction. Remember that the lines are open collector, so anything can hold the SDA line low (...
Posted on May 17, 2011 at 13:06I have an LCD peripheral connected to the FSMC SRAM bus (EVAL3210E board, ISI9320 LCD controller). The FSMC parameters handle address and data setup times, but there doesn't seem to be anything for bus cycle times (100...
Posted on May 17, 2011 at 13:06In the SPI_SR register is a CRCERR flag, used (I presume) to show a CRC error on SPI receiving a block of data. At what point does the CRC flag get set? How does the CRC unit know when the SPI port is finished transfer...
