STR71 stop mode requires clock config when exit from stopmode

[virtualashok]

Posted on August 13, 2007 at 07:27

STR71 stop mode requires clock config when exit from stopmode

[virtualashok]

Posted on July 13, 2007 at 06:04

Dear all,

I enter in to stop mode with following configuration 1) MVR is turned off 2) Flash controller is turned off When I wakeup using the external wakeupline, my UART and other terminals does not function properly the baud rates are changed need to reconfigure my clock for the proper functioning. Can any one help me in finding the reason.#

[kaouther]

Posted on August 13, 2007 at 07:27

Hello,

returning from stop does not require to re-configure the system clock. The only requirement is a delay of 2048 CLK clock periods derived from the external oscillator after the Stop mode wakeup event and then you get the right system behavior. ;)