removed SRAM backup feature?

[brunodavidmail]

Posted on February 17, 2009 at 05:02

removed SRAM backup feature?

[brunodavidmail]

Posted on May 17, 2011 at 11:52

Hello,

I started to evaluate these microcontrollers for a project. The project should include a non-volatile SRAM and I wonder why the battery backup feature was removed ? Could somebody tell me: 1) The problem that made manufacturer to recently retract battery backup of SRAM - feature from datasheets. I would like to weight if I could override somehow that problem in order to have that non-volatile memory on-chip. 2) Microcontrollers shipped from now on still do include the hardware that was intended to support SRAM backup or it was completely ousted/deactivated from silicon too ? A new revision ? I couldn't find any precise answer to my questions in existing messages except maybe those depicting the case when backup voltage larger than SRAM nominal voltage causes SRAM to unexpectedly become inaccessible to MCU. Thank you BD [ This message was edited by: brunodavidmail on 08-02-2009 16:22 ]

[jagtap]

Posted on May 17, 2011 at 11:52

This feature is removed because of battery backup RAM corruption in some cases.

The mentioned problem was found only with one customer application using PSD813F2. The symptoms was following: The PSD device was configured to use battery backup of RAM using PC2 pin. Than the main voltage was switched off and RAM was supplied by the battery. Problem occurs when the main supply voltage was switched ON again. Some percentage of this devices shows glitch (voltage drop out) on PC2 pin (battery backup) which in some case leads to RAM corruption. It was always linked with some particular conditions. The devices has to be erased by DATA I/O programming tool and later soldered with connected battery by soldering wave. This problem has never been observed on the bench with devices programmed by JTAG interface. The design analysis says that the problem is caused by the reading of pin configuration from the flash during the Vcc ramp up (about 1.7 V) when the flash is not fully ready. In other words, it means that there is not sufficient margin to cover potential problems with not optimally programmed flash. During solving of this problem with customer we found two workarounds which minimize possible RAM corruption. One is software one which is based on disabling RAM access by using !pdn & _reset signal in the rs0 chip select equation, see attached picture. Hardware workaround speed up the main voltage ramp up by few external components, see attached schematics. As ST cannot be 100% sure that this workarounds solve this problem and we cannot confirm that this is linked only with PSD813F2 we decide to remove this backup feature from our xPSD datasheets (Jan 09). Somnath Jagtap.

[jagtap]

Posted on May 17, 2011 at 11:52

This feature is removed because of battery backup RAM corruption in some cases.

The mentioned problem was found only with one customer application using PSD813F2. The symptoms was following: The PSD device was configured to use battery backup of RAM using PC2 pin. Than the main voltage was switched off and RAM was supplied by the battery. Problem occurs when the main supply voltage was switched ON again. Some percentage of this devices shows glitch (voltage drop out) on PC2 pin (battery backup) which in some case leads to RAM corruption. It was always linked with some particular conditions. The devices has to be erased by DATA I/O programming tool and later soldered with connected battery by soldering wave. This problem has never been observed on the bench with devices programmed by JTAG interface. The design analysis says that the problem is caused by the reading of pin configuration from the flash during the Vcc ramp up (about 1.7 V) when the flash is not fully ready. In other words, it means that there is not sufficient margin to cover potential problems with not optimally programmed flash. During solving of this problem with customer we found two workarounds which minimize possible RAM corruption. One is software one which is based on disabling RAM access by using !pdn & _reset signal in the rs0 chip select equation, see attached picture. Hardware workaround speed up the main voltage ramp up by few external components, see attached schematics. As ST cannot be 100% sure that this workarounds solve this problem and we cannot confirm that this is linked only with PSD813F2 we decide to remove this backup feature from our xPSD datasheets (Jan 09). Somnath Jagtap.