Posted on June 20, 2004 at 16:12Hi Jose,
Not sure what your problem is with the Tx/Rx control line, but it simply controls the mode of operation of the chip, switching between low power receiver mode and high power transmit mode. The idea is that you idle in Rx (low power mode) and switch to Tx mode only when you wish to transmit data. Setting the Rx/Tx line to logical zero switches ON the Power Line Tranceiver (output) stage of the chip and enbles the 123.25KHz FSK carriers signal.
Note there's a 3.2msec settling delay on the carrier waveform and you shouldn't start transmitting data until the carrier is stable, (see page 20 of the datasheet).
As you've enabled preable detection on the chip, the CD_PD line goes low when a four byte string of AA, AA, AA, AA or 55, 55, 55, 55 is received by the chip. [The chip needs to be in Rx mode, with Rx/Tx = logical 1].
In Rx mode there's a detection delay due to the chip and an additional digital filtering delay. [Note the control register settings for the digital filter extend this delay].
The CD_PD line goes low after the delay period, (i.e. when the data starts to be clocked out of the serial port (SPI) master) and the low edge of CD_PD is in synch with the first preable byte.
The CD_PD line will stay low while the complete message is clocked out, (i.e. for all bytes of the message) and returns high afterwards.
The I also had problems with extra CLR/T clock pulses and never got the chip to work with error free data. STM told me that the chip was okay, but I think there's a hardware bug in the chip.
Good luck
