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EMI Memory alignment (WE.0/WE.1/A0)

al1
Associate
Posted on March 02, 2006 at 13:49

EMI Memory alignment (WE.0/WE.1/A0)

1 REPLY 1
al1
Associate
Posted on March 02, 2006 at 13:49

I am working on an application with an STR710FZ2 interfacing to an external SST flash/SRAM combo chip (SST34HF3284)

I'm trying to work out the addressing lines.

One problem, the SST chip has seperate LowerByte/UpperByte selects on the SRAM (which work with the CS1 line). Unfortunately for BOTH read and write. Originally, we had tied the STR7 WE.0 and WE.1 to LBS and UBS, but that doesn't allow reading with the SST chip

Now currently I have tied both lines low. - I thought by activating BOTH in the SRAM chip, and setting the EMI register to 16bit accesses, that both devices would only read/write in 16bit mode and it would work.

However, that doesn't seem to be working. Currently in my code, when I write an 8bit value to 0x62000000, it reads back fine. when I write to 0x62000001, it reads back what was in 0x62000000.

if an external memory device is configured to operate in 16bit mode, what combinations of control access must be planned for in the memory? (I didn't see any ''8bit access on 16bit memory device'' example timing)

Any ideas on this 16bit addressing setup?

Cheers,

Al