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al1 · 2006-03-02

Posted on March 02, 2006 at 13:49EMI Memory alignment (WE.0/WE.1/A0)

al1 · 2006-03-02

Posted on March 02, 2006 at 13:49I am working on an application with an STR710FZ2 interfacing to an external SST flash/SRAM combo chip (SST34HF3284) I'm trying to work out the addressing lines. One problem, the SST chip has seperate LowerByte/UpperB...

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EMI Memory alignment (WE.0/WE.1/A0)

Re: EMI Memory alignment (WE.0/WE.1/A0)