BSPI question

per2 · ‎2004-12-08

Posted on December 09, 2004 at 05:57

BSPI question

per2 · ‎2004-12-06

Posted on December 07, 2004 at 08:14

We are designing our hardware right now and have one question regarding the BSPI pin /SS.

We will use one of the BSPI ports to clock data into and out of a large shift register. For that we will use the SCLK, MISO and MOSI pins (in Master mode).

My question is:

Can the /SS then pin be used as a general output? Or will the ARM make it go low when I'm tranceiving data in Master mode?

In the refernce manual page 266 it says:

The /SS on the master must be asserted high</ul>
But picture 65 in the refernce manual page 265 indicates that the /SS pin is an input.

I want to use it as is a LATCH output signal to my shift register.
This means that it will be high all the time except when I make a short latch pulse. This pulse will only be present after I've have shifted the data.

Regards
/Yxan/

hichem2 · ‎2004-12-07

Posted on December 07, 2004 at 13:47

Hi Yxan,

It's not possible to use the SSN pin as you described it in your message, the STR71x reference manual note that the the /SS pin must be asserted high on the master mode ,and this in order to avoid to have two master device at the same time.

I hope that can help you

Best Regards.

Hich ;)

per2 · ‎2004-12-07

Posted on December 08, 2004 at 05:59

Hi Hich,

Ok, I see that it says that the /SS pin must be asserted high.

But why???

You say: ''to make sure there isn't more than one master at the same time''

But I still dont understand,

I slave mode the /SS pin is used as an input - OK

I master mode the pin is not used but it must kept in high state.

WHY????? :o

Sorry for not just accepting it, I want to know why the pin cannot be used.

Yxan

hichem2 · ‎2004-12-08

Posted on December 09, 2004 at 05:23

Hi Yxan,

In master mode this pin is used to detect that more than one device has acted as a Master simultaneously on the BSPI bus.

The BSPI, configured as a master, will generate a Bus Error condition.

This error is defined as a condition where the Slave Select line goes active low when the module is configured as a Master. This indicates contention in that more than one node on the BSPI bus is attempting to function as a Master.

Best Regards.

HICH :p

per2 · ‎2004-12-08

Posted on December 09, 2004 at 05:57

OK, now I understand.

Unfortunally this means one pin less to play around with.

Thanx for the clarification

/Yxan/