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Why I can't set HOST_DEBUG_EN in TnDCM CR register on SR6P7G7C7? I use key 0xE0E05FE0 to unlock it, but bit doesn't change the value. External debugger is not connected.

Oleksandr_Gonchar
Associate II

I'm working with SR6P7G7C7 and I would like to start CoreSight trace from MCU without external tools. I configured Core0 ETM and TMC ETR, but trace doesn't start. I assume the problem is in TnDCM_CR register, I am not able to set HOST_DEBUG_EN. I use the key like below:

#define TnDCM_CR               (*(volatile uint32_t*)(0x7100c000))
 
TnDCM_CR = 0xE0E05FE0;
TnDCM_CR = 0x10000000;

but it doesn't change the value in register.

1 ACCEPTED SOLUTION

Accepted Solutions

Hello,

If JCOMP is floating and debugger is not connected, this bit is used to enable host based debugging. By default when debugger is not connected (and JCOMP is floating or connected to GND), debug and trace logic remains in reset. Setting this bit to HIGH will bring the debug and trace resources out-of-reset. When any CPU or non-CPU Bus Master needs to access the debug and trace

resources it should first program this bit to HIGH. HOST_DEBUG_EN

overwrites the JCOMP or TAP select signal connected to DAP reset.

0 When debugger is not connected then host based debugging is not

enabled. JCOMP to DAP is low.

1 When debugger is not connected then host based debugging is

enabled. JCOMP to DAP is high.

So, if you connect the hardware debugger tool means that JCOMP is configured to enable device debug part, so it will work independently by this bit configuration.

Regards,

Salvo

View solution in original post

10 REPLIES 10

What is the JCOMP configuration of the DAP connector? As the debugger is not connected, is it floating? Or do you force this pin to 1. If you don't use any hardware configuration, can you try to set a logic value 1 on JCOMP pin?

Oleksandr_Gonchar
Associate II

JCOMP pushed up


_legacyfs_online_stmicro_images_0693W00000bkfEiQAI.png

JCOMP pushed up

Are you able to read the TnDCM SR?

What is the flow that you followed before accessing CR?

Christian N
ST Employee

Hi Oleksandr,

Thank you for contacting STMicroelectronics. Your inquiry is being treated directly via the online support team.

Should anyone have similar technical inquiries regarding an ST device, please do not hesitate to submit your requests directly at my.st.com/ols.

Kind Regards,

Christian

ST Support

Yes, I am able to read it out and result looks strange for me.

TnDCM SR has always the same value 0x311303 despite debugger connected or not connected. I read it by MCU and send the value over UART.

About flow, I tried set it in startup code before the Exception level is switched in System Mode and before MPU initialisation, but it didn't help. So I put the code direct after vector table setup, the code is below:

    ldr     r0, =#0x7100c000
    ldr     r1, =#0xE0E05FE0
    str     r1, [r0]
    ldr     r1, =#0x10000000
    str     r1, [r0]

But it didn't help in general.

I assume it worked only once, but after that I lost a control over my board, the debugger now doesn't see JTAG connection with my Stellar, it looks like now it is bricked. I guess it was bad idea put this code in startup. But before the board was bricked, I ran this code many times without any effect. For the moment I have a new board, but this code doesn't work also.

Hello,

It could be to MPU configuration. I suggest to put code in EL2 after MPU configuration for.

I don't think the code can brick the device.


ST Restricted

OK, I will try it.

I have a question regarding TnDCM, if I enable bit HOST_DEBUG_EN is it possible to connect external debugger for debugging? We would like to run Trace always by MCU, but be able to connect External Debugger (Lauterbach in our case) over JTAG for debugging, is it possible?

Hello,

If JCOMP is floating and debugger is not connected, this bit is used to enable host based debugging. By default when debugger is not connected (and JCOMP is floating or connected to GND), debug and trace logic remains in reset. Setting this bit to HIGH will bring the debug and trace resources out-of-reset. When any CPU or non-CPU Bus Master needs to access the debug and trace

resources it should first program this bit to HIGH. HOST_DEBUG_EN

overwrites the JCOMP or TAP select signal connected to DAP reset.

0 When debugger is not connected then host based debugging is not

enabled. JCOMP to DAP is low.

1 When debugger is not connected then host based debugging is

enabled. JCOMP to DAP is high.

So, if you connect the hardware debugger tool means that JCOMP is configured to enable device debug part, so it will work independently by this bit configuration.

Regards,

Salvo