Im working for bootloader on SPC564A80B4. Facing issues in system clock generation

Mahesh Chamaraja · ‎2017-01-21

Posted on January 22, 2017 at 06:58

Hello, I configured in enhanced mode for system clock generation, our input clock is 40Mhz external crystal and need to generate 150Mhz system clock. Since hardware is not supported to check CLKOUT pin for system clock, we configured SCK clock for calculating system clock.

In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
For below configuration, code is running some exceptional condition. No system clock generation.
FMPLL.ESYNCR2.R = 0x00000001;
FMPLL.ESYNCR1.R = 0xF005002D
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
FMPLL.ESYNCR2.R = 0x00000000;

NOTE: For above configuration the parameters values EPREDIV, ERFD and EMFD is not satisfying for 150Mhz system clock generation if we substitute in enhanced mode formula. Im confused!!!!!

In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
For below configuration, code is running some exceptional condition. No system clock generation.
FMPLL.ESYNCR2.R = 0x00000000;
FMPLL.ESYNCR1.R = 0xF005002D;
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
FMPLL.ESYNCR2.R = 0x00000000;

In below code we referred reference manual of SPC564A80B4. Here we not facing problem debug port fail. The code is free running in debug condition.
For below configuration, system clock is 72Mhz
FMPLL.ESYNCR2.R = 0x00000001;
FMPLL.ESYNCR1.R = 0xF005002D
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
FMPLL.ESYNCR1.R |= 0x70000000;

In below code we referred reference manual of SPC564A80B4, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
For below configuration, system clock is 150Mhz.
FMPLL.ESYNCR2.R = 0x00000000;
FMPLL.ESYNCR1.R = 0xF005002D
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
FMPLL.ESYNCR1.R |= 0x70000000;

Please do needful and give us solution resolve this issue, the project is in critical condition. If any documents related to issue please do share to my ID below mentioned.

Regards

Mahesh chamaraja

Office ID :

mailto:mahesh.chamaraja@kpit.com

Phone No : +917259205624

##clock ##spc56 ##fmpll

Erwan YVIN · ‎2017-01-31

Posted on January 31, 2017 at 09:43

Hello Mahesh ,

For this , you should contact TRACE32 Lauterbach in parallel.

I have no issue with PLS UDE using your configuration

See my clock configuration below

/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
 * @brief Disables the clocks initialization.
 */
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
#define SPC5_NO_INIT FALSE
#endif
/**
 * @brief Clock bypass.
 * @note If set to @p TRUE then the PLL is not started and initialized, the
 * external clock is used as-is and the other clock-related settings
 * are ignored.
 */
#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
#define SPC5_CLK_BYPASS FALSE
#endif
/**
 * @brief Disables the overclock checks.
 */
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
#define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
 * @brief External clock pre-divider.
 * @note Must be in range 1...
 */
#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_CLK_PREDIV_VALUE 2U
#endif
/**
 * @brief Multiplication factor divider.
 * @note Must be in range ..
 */
#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
#define SPC5_CLK_MFD_VALUE 75U
#endif
/**
 * @brief Reduced frequency divider.
 */
#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
#define SPC5_CLK_RFD RFD_DIV2
#endif�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?
/**
 * @brief SPC563 clocks and PLL initialization.
 * @note This function must be invoked only after the system reset.
 *
 * @special
 */
void spc_clock_init(void) {
#if (SPC5_NO_INIT == FALSE)
 /* PLL activation.*/
 FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
 FMPLL.ESYNCR1.B.CLKCFG &= 1U; /* Bypass mode, PLL off.*/
#if (SPC5_CLK_BYPASS == FALSE)
 FMPLL.ESYNCR1.B.CLKCFG |= 2U; /* PLL on. */
 FMPLL.ESYNCR1.B.EPREDIV = (uint8_t)SPC5_CLK_PREDIV;
 FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
 FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
 while (FMPLL.SYNSR.B.LOCK == 0U) {
 }
 FMPLL.ESYNCR1.B.CLKCFG |= 4U; /* Clock from the PLL. */
#endif /* !SPC5_CLK_BYPASS */
/* SYS Clock Divider setting.*/
#if (SPC5_SIU_SYSDIV_BYPASS == TRUE)
 SIU.SYSDIV.B.BYPASS = 1U;
#else
 SIU.SYSDIV.B.BYPASS = 0U;
 SIU.SYSDIV.B.SYSCLKDIV = (uint8_t)SPC5_SIU_SYSDIV_SYSCLKDIV;
#endif
/* Setting up RAM/Flash wait states and the prefetching bits.*/
 ECSM.MUDCR.R = SPC5_RAM_WS;
 FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
 FLASH_A.BIUCR2.R = 0;
#if !defined(_SPC564A70_)
 /* The second controller is only present in Andorra 3M or 4M.*/
 FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
 FLASH_B.BIUCR2.R = 0;
#endif /* !defined(_SPC564A70_) */
#endif /* !SPC5_NO_INIT */
}�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

Best regards

Erwan

Mahesh Chamaraja · ‎2017-01-31

Posted on January 31, 2017 at 15:39

Hello Erwan,

Still I facing same problem debug port fail that to only main function and PLL initialisation in my code.

One more important thing i reduced PLL from 150Mhz to 137Mhz, its working fine. why these changes making impact?

Regards

Mahesh

Erwan YVIN · ‎2017-02-01

Posted on February 01, 2017 at 17:04

Hello ,

Have you contacted TRACE32 Lautechbach ppc ?

I have A70L7 Discovery Board and Mini-Module A70L7.

No Pb on 150Mhz

Did you try my clock configuration by using the Bit Configuration not a Full Registers setting ?

(cf Last Screenshot)

Best regards

Erwan

Erwan YVIN · ‎2017-02-01

Posted on February 01, 2017 at 17:15

you should assert EMODE and program EPREDIV / EMFD by bits

Otherwise the PLL can not locked

Could you respect 1) 2) 3) 4) ?

Best regards

Erwan

Mahesh Chamaraja · ‎2017-02-01

Posted on February 02, 2017 at 04:41

Hello,

If I reduce PLL clock frequency, I'm able to achieve free running. Since even I tried with different setting and on different lauterbach setup .

I think no problem with Lauterbach

Regards

Mahesh

Mahesh Chamaraja · ‎2017-02-01

Posted on February 02, 2017 at 04:48

Hello Erwan,

Yes above steps i followed to program the FMPLL and engage normal mode but '3rd' point not configured, frequency modulation not required.

Regards

Mahesh

Erwan YVIN · ‎2017-02-02

Posted on February 02, 2017 at 09:53

Hello Mahesh ,

Could you send me your clock configuration ?

The first configuration is not correct.

You have asserted your clock by full registers not by bits.

Best regards

Erwan

Mahesh Chamaraja · ‎2017-02-02

Posted on February 02, 2017 at 13:44

Hello Erwan,

Please check our clock configuration. Mhz

Regards

Mahesh

Mahesh Chamaraja · ‎2017-02-08

Posted on February 09, 2017 at 07:44

Hello Erwan,

I'm waiting for reply. check above clock settings.

Best regards

Mahesh

Erwan YVIN · ‎2017-02-16

Posted on February 16, 2017 at 09:29

Hello Mahesh ,

I have reproduced your issue.

in putting your clock settings, the PLL can not be locked.

SPC564Axx should support this clock settings.

I am checking with soc functional valid team.

Best regards

Erwan