Im working for bootloader on SPC564A80B4. Facing issues in system clock generation

[Mahesh Chamaraja]

Posted on January 22, 2017 at 06:58

Hello,  I configured in enhanced mode for system clock generation, our input clock is 40Mhz external crystal and need to generate 150Mhz  system clock. Since hardware is not supported to check CLKOUT pin for system clock, we configured SCK clock for calculating system clock.

• In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.For below configuration, code is running some exceptional condition. No system clock generation.FMPLL.ESYNCR2.R = 0x00000001;FMPLL.ESYNCR1.R = 0xF005002Dwhile (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */ FMPLL.ESYNCR2.R = 0x00000000;

NOTE: For above configuration the parameters values EPREDIV, ERFD and EMFD is not satisfying for 150Mhz system clock generation if we substitute in enhanced mode formula. Im confused!!!!!

•  In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32. For below configuration, code is running some exceptional condition. No system clock generation. FMPLL.ESYNCR2.R = 0x00000000; FMPLL.ESYNCR1.R = 0xF005002D; while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */ FMPLL.ESYNCR2.R = 0x00000000;

• In below code we referred reference manual of SPC564A80B4. Here we not facing problem debug port fail. The code is free running in debug condition.For below configuration, system clock is 72MhzFMPLL.ESYNCR2.R = 0x00000001;FMPLL.ESYNCR1.R = 0xF005002Dwhile (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */ FMPLL.ESYNCR1.R |= 0x70000000;

• In below code we referred reference manual of SPC564A80B4, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.For below configuration, system clock is 150Mhz.FMPLL.ESYNCR2.R = 0x00000000;FMPLL.ESYNCR1.R = 0xF005002Dwhile (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */ FMPLL.ESYNCR1.R |= 0x70000000;

Please do needful and give us solution resolve this issue, the project is in critical condition. If any documents related to issue please do share to my ID below mentioned.

Regards 

Mahesh chamaraja

Office ID : 

mailto:mahesh.chamaraja@kpit.com

Phone No : +917259205624

##clock ##spc56 ##fmpll

[Erwan YVIN · Accepted solution]

Posted on February 21, 2017 at 10:41

Hello Mahesh ,

sorry the RM is not cleared

You should respect some steps

Step 1

Support for 50MHz system clock generation

The oscillator and PLL support generation of a 150 MHz system clock while using the 40 MHz crystal required for FlexRay operation. A possible PLL configuration is shown below: �?

Input clock (crystal frequency): 40 MHz

�? EPREDIV/IDF divider = /8 (1–15 range supported) �? EMFD/NDIV loop divider = 80 (32–96 supported) �? VCO clock out = 300 MHz (256–512 MHz range supported) �? ERFD/ODF output divider = /2 (/2, /4, /8, /16 supported) �? SYSDIV divider = /1 (/1, /2, /4, /8, /16 supported) �? System clock = 50 MHz

Step 2

wait for Lock the PLL

Step 3

Support for 50MHz system clock generation

The oscillator and PLL support generation of a 150 MHz system clock while using the 40 MHz crystal required for FlexRay operation. A possible PLL configuration is shown below: �?

Input clock (crystal frequency): 40 MHz

�? EPREDIV/IDF divider = /8 (1–15 range supported) �? EMFD/NDIV loop divider = 60 (32–96 supported) �? VCO clock out = 300 MHz (256–512 MHz range supported) �? ERFD/ODF output divider = /2 (/2, /4, /8, /16 supported) �? SYSDIV divider = /1 (/1, /2, /4, /8, /16 supported) �?

System clock = 150 MHz

Step 4

wait for Lock the PLL

==> It is ok for my side

/**
 * @brief SPC563 clocks and PLL initialization.
 * @note All the involved constants come from the file @Community memberoard.h and
 * @p hal_lld.h
 * @note This function must be invoked only after the system reset.
 *
 * @special
 */
void spc_clock_init(void) {

#if !SPC5_NO_INIT
 /* PLL activation.*/
 FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
 FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
#if !SPC5_CLK_BYPASS
 FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
 FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
 FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
 FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
 while (!FMPLL.SYNSR.B.LOCK)
 ;
 FMPLL.ESYNCR1.B.EMFD = 60;
 while (!FMPLL.SYNSR.B.LOCK)
 ;
 FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
#endif /* !SPC5_CLK_BYPASS */
 /* SYS Clock Divider setting.*/
#if (SPC5_SIU_SYSDIV_BYPASS == TRUE)
 SIU.SYSDIV.B.BYPASS = 1U;
#else
 SIU.SYSDIV.B.BYPASS = 0U;
 SIU.SYSDIV.B.SYSCLKDIV = (uint8_t)SPC5_SIU_SYSDIV_SYSCLKDIV;
#endif
 /* Setting up RAM/Flash wait states and the prefetching bits.*/
 ECSM.MUDCR.R = SPC5_RAM_WS;
 FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
 FLASH_A.BIUCR2.R = 0;
#if !defined(_SPC564A70_)
 /* The second controller is only present in Andorra 3M or 4M.*/
 FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
 FLASH_B.BIUCR2.R = 0;
#endif /* !defined(_SPC564A70_) */
 /* CAN Clock Divider setting.*/
 SIU.SYSDIV.B.CAN_SRC = (uint8_t)SPC5_SIU_SYSDIV_CAN_SRC; 
#endif /* !SPC5_NO_INIT */
}
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Best regards

Erwab

[Mahesh Chamaraja]

Posted on March 14, 2017 at 09:34

Hello Erwan,

Sorry for the delay

Can I know the values for this macros?

SPC5_FLASH_WS
SPC5_FLASH_BIUCR