The spec sheet contradicts itself on this question. What does the chip actually expect/do?
SPI is an "big endian" protocol at the bit level, where the MSb of each byte is transmitted first on the wire and the LSb of each byte is transmitted last. Looking at the SPI timing diagram in the LSM6DS3's spec sheet, Figure 8, page 37, DocID 026899 Rev 10, the SDI and SDO bits are shown being transmitted with their MSb's first. For address, input data, and output data, the first bits are shown as R/W, DI7, and DO7 respectively. This appears to comply with the SPI industry standard.
However, in the text below Figure 8 on the same page, it says "the first bit (bit 0) starts at the first falling edge of SPC...". It then goes on to describe the bits, *starting* with "bit 0: R/W bit".
Thus the diagram and the text appear to contradict each other. I can spin this into "agreement" by saying that the text's "bit 0" is the figure's "bit 7" but that's really stretching things.
I'm asking because we're having a hard time getting the LSM6DS3 to communicate over SPI. Communication to other SPI devices is working great, it's just the LSM6DS3 that is having trouble, so we started looking for anything "special" about the LSM6DS3 that might be "different" and we ran across this oddity in the spec sheet.
Can anyone confirm which bit the LSM6DS3 transmits and receives first? Most specifically, is the R/W bit transmitted at the beginning of the address byte, or at the end of the address byte?
Thank you!
