LIS2DH12 INT1 no signal

[Gonederra_CEIT]

Good morning,

I am having issues with the INT1 pin on the LIS2DH12. I have been trying to make it to work for Watermark, Overrun or ZYXDA, but none of these events trigger any interrupt on the INT1 pin. When polling the Watermark Level, the FIFO Overrun or the new data available register though, I can see that they are working as intended.

Here is the configuration code, in case it helps or anyone can see an issue:

lis2dh12_block_data_update_set(&dev_ctx, PROPERTY_ENABLE);					/* Enable Block Data Update. */
lis2dh12_data_rate_set(&dev_ctx, LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP);	/* Set Output Data Rate to 1Hz. */
lis2dh12_full_scale_set(&dev_ctx, LIS2DH12_2g);								/* Set full scale to 2g. */
//lis2dh12_temperature_meas_set(&dev_ctx, LIS2DH12_TEMP_ENABLE);			/* Enable temperature sensor. */
lis2dh12_operating_mode_set(&dev_ctx, LIS2DH12_LP_8bit);					/* Set device in continuous mode with 12 bit resol. */
lis2dh12_fifo_mode_set(&dev_ctx, LIS2DH12_BYPASS_MODE);						/* Set FIFO mode to Bypass mode */

FIFO Operation Mode Configuration:

lis2dh12_fifo_watermark_set(&dev_ctx, 0);				/* Set FIFO watermark to 0 */
lis2dh12_fifo_mode_set(&dev_ctx, LIS2DH12_BYPASS_MODE);	/* Set FIFO mode to Bypass mode */
lis2dh12_fifo_mode_set(&dev_ctx, LIS2DH12_FIFO_MODE);	/* Set FIFO mode to FIFO mode */

/* Set FIFO Overrun interrupt on INT1 pin */
lis2dh12_read_reg(&dev_ctx, LIS2DH12_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);	/* Read the current CTRL_REG3 settings into the reg variable */
ctrl_reg3.i1_overrun = PROPERTY_ENABLE;	/* Disable the I1_Overrun interrupt on the INT1 pin */
lis2dh12_write_reg(&dev_ctx, LIS2DH12_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);	/* Write the new settings back to CTRL_REG3 */
/* END OF Set FIFO Overrun interrupt on INT1 pin */

/* Set FIFO watermark latch enable on INT1 pin */
lis2dh12_read_reg(&dev_ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);	/* Read the current CTRL_REG5 settings into the reg variable */
ctrl_reg5.lir_int1 = PROPERTY_ENABLE;	/* Disable the LIR_INT1 interrupt on the INT1 pin */
lis2dh12_write_reg(&dev_ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);	/* Write the new settings back to CTRL_REG5 */
/* END OF Set FIFO watermark latch enable on INT1 pin */

/* Enable FIFO */
lis2dh12_fifo_set(&dev_ctx, PROPERTY_ENABLE);

Stream Mode Configuration:

lis2dh12_fifo_watermark_set(&dev_ctx, FIFO_WATERMARK - 1);		/* Set FIFO watermark to FIFO_WATERMARK */
lis2dh12_fifo_mode_set(&dev_ctx, LIS2DH12_BYPASS_MODE);			/* Set FIFO mode to Bypass mode */
lis2dh12_fifo_mode_set(&dev_ctx, LIS2DH12_DYNAMIC_STREAM_MODE);	/* Set FIFO mode to FIFO mode */

/* Set FIFO watermark interrupt on INT1 pin */
lis2dh12_read_reg(&dev_ctx, LIS2DH12_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);	/* Read the current CTRL_REG3 settings into the reg variable */
ctrl_reg3.i1_wtm = PROPERTY_ENABLE;	/* Enable the IA1 interrupt on the INT1 pin */
lis2dh12_write_reg(&dev_ctx, LIS2DH12_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);	/* Write the new settings back to CTRL_REG3 */
/* END OF Set FIFO watermark interrupt on INT1 pin */

/* Set FIFO watermark latch enable on INT1 pin */
lis2dh12_read_reg(&dev_ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);	/* Read the current CTRL_REG5 settings into the reg variable */
ctrl_reg5.lir_int1 = PROPERTY_ENABLE;	/* Enable the LIR_INT1 interrupt on the INT1 pin */
lis2dh12_write_reg(&dev_ctx, LIS2DH12_CTRL_REG5, (uint8_t*)&ctrl_reg5, 1);	/* Write the new settings back to CTRL_REG5 */
/* END OF Set FIFO watermark latch enable on INT1 pin */

/* Enable FIFO */
lis2dh12_fifo_set(&dev_ctx, PROPERTY_ENABLE);

No FIFO Mode Configuration

lis2dh12_fifo_watermark_set(&dev_ctx, 0);				/* Set FIFO watermark to 0 */
lis2dh12_fifo_mode_set(&dev_ctx, LIS2DH12_BYPASS_MODE);	/* Set FIFO mode to Bypass mode */
lis2dh12_fifo_set(&dev_ctx, PROPERTY_DISABLE);	/* Disable FIFO */

/* Set ZYXDA interrupt on INT1 pin */
lis2dh12_read_reg(&dev_ctx, LIS2DH12_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);	/* Read the current CTRL_REG3 settings into the reg variable */
ctrl_reg3.i1_zyxda = PROPERTY_ENABLE;	/* Enable the I1_ZYXDA interrupt on the INT1 pin */
lis2dh12_write_reg(&dev_ctx, LIS2DH12_CTRL_REG3, (uint8_t*)&ctrl_reg3, 1);	/* Write the new settings back to CTRL_REG3 */
/* END OF Set ZYXDA interrupt on INT1 pin */

After this configuration, whenever I poll the individual register for knowing if watermark level has been achieved, or FIFO is full or new data is available, the value is answered correctly. Yet, whenever I poll the interrupt source with:

lis2dh12_int1_gen_source_get(&dev_ctx, &interrupt);

It never comes as true. Also, looking with the oscilloscope, INT1 pin always stays 0. Even when I change INT pin polarity with:

/* Set INT1 and INT2 polarity to Active-Low */
lis2dh12_read_reg(&dev_ctx, LIS2DH12_CTRL_REG6, (uint8_t*)&ctrl_reg6, 1);	/* Read the current CTRL_REG6 settings into the reg variable */
ctrl_reg6.int_polarity = PROPERTY_DISABLE;	/* Disable the LIR_INT1 interrupt on the INT1 pin */
lis2dh12_write_reg(&dev_ctx, LIS2DH12_CTRL_REG6, (uint8_t*)&ctrl_reg6, 1);	/* Write the new settings back to CTRL_REG5 */
/* END OF Set INT1 and INT2 polarity to Active-Low */

It never triggers. The INT1 pin is floating, is not connected anywhere in the microcontroller (as I am now working with the STEVAL-MKI135V1, so it is not getting pulled to 0 anywhere.

Can anyone help me? 

Lots of thanks in advance.