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i2c not working in release mode IAR

AndyR1
Senior

Hello,

I would to access to i2c devices with bluenrg-355MT, I use functions from BlueNRG-LP DK 1.0.0, in bluenrg_lp_evb_i2c files. When I Download and Debug, i2c works fine, but in release mode there is no i2c signals.

Here my code to detect light sensor :

BSP_I2C_Init();
 
HAL_StatusTypeDef ret;
 
ret = HAL_I2C_IsDeviceReady(&hi2cx, 0x10<<1, 1, 10);
if( ret != HAL_OK )
    printf("Device not present.\r\n");
else
    printf("Light sensor detected.\r\n");

Whatever the parameters, there is no signals.

I2C is configured like this :

/* Initialize the GPIOs associated to the I2C port */
BSP_I2C_DATA_GPIO_CLK_ENABLE();
LL_GPIO_SetPinMode(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinSpeed(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinOutputType(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, LL_GPIO_OUTPUT_OPENDRAIN);
LL_GPIO_SetPinPull(BSP_I2C_DATA_GPIO_PORT, BSP_I2C_DATA_PIN, BSP_I2C_DATA_GPIO_PULL);
BSP_I2C_DATA_GPIO_AF();
 
BSP_I2C_CLK_GPIO_CLK_ENABLE();
LL_GPIO_SetPinMode(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinSpeed(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinOutputType(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, LL_GPIO_OUTPUT_OPENDRAIN);
LL_GPIO_SetPinPull(BSP_I2C_CLK_GPIO_PORT, BSP_I2C_CLK_PIN, BSP_I2C_CLK_GPIO_PULL);
BSP_I2C_CLK_GPIO_AF();
 
/* Initialize the I2C clock */
BSP_I2C_CLK_ENABLE();
 
LL_I2C_Disable(BSP_I2C);
  
/* Configure the SDA setup, hold time and the SCL high, low period
* For Fast-mode 400 kHz, PRESC | 0h | SCLDEL | SDADEL | SCLH | SCLL
*                          1h  | 0h |    3h  |   2h   |  03h |  09h
*/
LL_I2C_SetTiming(BSP_I2C, 0x10320309);
 
/* Enable Clock stretching */
LL_I2C_EnableClockStretching(BSP_I2C);
 
/* Enable Peripheral in I2C mode */
LL_I2C_SetMode(BSP_I2C, LL_I2C_MODE_I2C);
 
/* Enable the I2C peripheral */
LL_I2C_Enable(BSP_I2C);

Its I2C1 CLK-PA0 DATA-PA1

Could debug mode force peripheral to work by enabling all clocks and power paths, so i forgot to enable something ? Or what the difference between release and debug in µC configuration point of view ?

Thanks for any help,

Andy.

1 ACCEPTED SOLUTION

Accepted Solutions
Sebastien DENOUAL
ST Employee

Hi @Community member​ ,

I guess this behavior is linked to PA0 and PA1. LEt me share my hypothesis here.

I suppose you are using ST-Link as debug/flash probe.

In fact, PA0 and PA1 are also JTAG pins.

ST-Link probe is sending a specific sequence leading to reconfiguration of PA1/PA0 for JTAG.

Unfortunately, this JTAG configuration can be cleaned only by a PowerOnReset. A HW_Reset does not affect JTAG config explaining behavior you noticed.

After flashing, if you perform a power on reset ( power off on your board), your I2C should be functional as per what you see in debug mode.

This specific sequence of SWD-to-JTAG is present at the end of any ST-Link operation such as debugging or also programming.

Only a power On sequence can erase JTAG configuration ...so a power on reset to restart the application is needed.

I know that this is very annoying to do power off and power on. So, in this case, I suggest to use another debugger as solution.

I could advise usage of the CMSIS DAP debugger as per default probe use on BlueNRG-LP eval board : STEVAL-IDB011V1 board.

FYI, you could try to get this one (of course it exists other references)

www.electrodragon.com/product/daplink-cmsis-dap-debugger-arm-cortex-stm32-mdk

You can also flash your binary using UART bootloader.

Regards,

Sebastien.

View solution in original post

3 REPLIES 3
Sebastien DENOUAL
ST Employee

Hi @Community member​ ,

I guess this behavior is linked to PA0 and PA1. LEt me share my hypothesis here.

I suppose you are using ST-Link as debug/flash probe.

In fact, PA0 and PA1 are also JTAG pins.

ST-Link probe is sending a specific sequence leading to reconfiguration of PA1/PA0 for JTAG.

Unfortunately, this JTAG configuration can be cleaned only by a PowerOnReset. A HW_Reset does not affect JTAG config explaining behavior you noticed.

After flashing, if you perform a power on reset ( power off on your board), your I2C should be functional as per what you see in debug mode.

This specific sequence of SWD-to-JTAG is present at the end of any ST-Link operation such as debugging or also programming.

Only a power On sequence can erase JTAG configuration ...so a power on reset to restart the application is needed.

I know that this is very annoying to do power off and power on. So, in this case, I suggest to use another debugger as solution.

I could advise usage of the CMSIS DAP debugger as per default probe use on BlueNRG-LP eval board : STEVAL-IDB011V1 board.

FYI, you could try to get this one (of course it exists other references)

www.electrodragon.com/product/daplink-cmsis-dap-debugger-arm-cortex-stm32-mdk

You can also flash your binary using UART bootloader.

Regards,

Sebastien.

AndyR1
Senior

Hello @Sebastien DENOUAL​ ,

Nice hypothesis, thank you very much. Indeed it works after power reset or after programming with UART bootloader. I guess there won't be this issue with an OTA manager.

Thanks,

Andy.

Sebastien DENOUAL
ST Employee

Hi @Community member​ ,

You're welcome.

I confirm no issue while using OTA manger - This JTAG config happens only while flashing using external ST-Link probe.

Regards,

Sebastien.