dma cause error in uart frame, bluenrgLP

[AndyR1]

Hello community,

I configured the uart dma in my project based on the project example USART_TxRx_DMA_Init, and stuck in frame errors, one of the errors is the end of the string seems to be swapped.

Sometimes there is no problem the end of the string is \r\n (0x0D 0x0A) and sometime its 0x0D 0xA0. This is because the dma ends before uart has finished, and another string is sent.

I modified the example project so that it continuously sends with few ms delay between each, and no error.

• How to prevent dma from overwriting previous string data without delay ? (using another IT ?)

I got the same issue with the example project and STEVAL-IDB011, you can see in above image, the spike is the dma IT.

[AndyR1]

If you want to try with the example project :

  while (1)
  {
      /*< INIT >*/
      LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_7, ubNbDataToTransmit);
      LL_DMA_ConfigAddresses(DMA1,  LL_DMA_CHANNEL_7, (uint32_t)aTxBuffer,
                             LL_USART_DMA_GetRegAddr(USART1, LL_USART_DMA_REG_DATA_TRANSMIT),
                             LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_CHANNEL_7));
      LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_7);
      LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_7);
      LL_USART_EnableDMAReq_TX(USART1);
      LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_7);
    
      /*< Wait end of DMA >*/
      //LL_GPIO_ResetOutputPin(GPIOA,LL_GPIO_PIN_12);
      while (ubTransmissionComplete != 1);
      //LL_GPIO_SetOutputPin(GPIOA,LL_GPIO_PIN_12);
      
      /*< Delay >*/
      for(uint32_t i = 0 ; i < 100000 ; i++);
      
      /*< Reset >*/
      LL_DMA_DisableIT_TC(DMA1, LL_DMA_CHANNEL_7);
      LL_DMA_DisableIT_TE(DMA1, LL_DMA_CHANNEL_7);
      LL_USART_DisableDMAReq_TX(USART1);
      LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_7);
      
      ubTransmissionComplete = 0;
  }

[Guenael Cadier · Accepted solution]

Dear @Community member​ 

The Transfer complete signal from DMA will occur as soon as the last data to be transmitted is loaded by DMA in USART Transmit register.

At this moment, the last data is not transmitted yet.

What could be done on DMA TC :

=> enable TCIE at USART level

=> when TC interrupt occurs, last data is properly transmitted.

Then ubTransmissionComplete could be set to 1.

Regards

[AndyR1]

Hello @Guenael Cadier​ it helps, thank you.