AEK-COM-ISOSPI1 L9963T MISO and clock out of sync

[Frank2201]

Greetings

I have weird situation with AEK-COM-ISOSPI1 and cannot figure out what is wrong. Maybe someone here is experienced with this device and can help me out.

I have absolute encoder with SPI. When i connect directly to uC all is working fine. Then i tried to use AEK-COM-ISOSPI1 and have next problem:

I can readout the encoder data just with command read, so i generate just clock to start readout from encoder. This works fine, because on encoder side i get correct data 0x9F45.

These data are transferred back to uC but here i get messy data from AEK-COM-ISOSPI1. I get data 0x5F61. When i look the SPI signals with logic analyzer i can see that MISO is not sync with CLK cycle. And encoder is always on the same position. 

Can anyone help me and tell what im doing wrong here.

My configuration is.

Encoder side:
NSLAVE=1
TxAMP=1
TXEN=1
ISOfreq=1
BNE=1
DIS=0
SPICLKFREQ=22kohm (8MHz)

Microcontroller side:
NSLAVE=0
TxAMP=1
TXEN=1
ISOfreq=1
BNE=/
DIS=0
SPICLKFREQ=/

Best regards

Frank

[SRomeo]

Let me help you checking what's wrong.

Use the scope to check SPI signals before and after ISOSPI transmission:

Compare those signals.
If the Signals are coherent, I think you have to adjust SPI software configuration of your Micro board n 2, because what changes is how each micro boards encode/decode data.

Best regards
Simone

[Frank2201]

OK, today i made measurements with oscilloscope on both sides in one time.

And then i find out when i played with oscilloscope probes.

When i removed probe from CLK test pin, the encoder side starts giving me correct data. Then i started to play around with probes and find out:

When probes were on CLK and MOSI pin - data not correct

When probes were only on CLK - data not correct

When probes were only on MOSI pin - data correct

Seems there are some disturbances in SPI signals but question is why the oscilloscope show OK signals on uC side  - only one clk cycle is data high and then encoder side gives me two clk cyles data high.

I will start to playing with pulldown resistor on MOSI line if i will get better results.

[Frank2201]

OK, playing with filtering. Included capacitor between GND and MOSI on uC side.

Now i get good data on encoder side. 

I will try with different values and then i go with higher baud rates.

Still dont understand why l9963t get sampled data at seventh and eight clock cycle on uC side.

Looks like the l9963t is configured that data gets sampled on falling edge CLK cycle, with included capacitor seems data rising is delayed and the voltage level is not high enough to sample it on falling edge CLK cycle. 

But Im sure that JP3 (TXEN) on encoder side is on 0 position. So, it means that is configured as data sampled on rising edge CLK cycle (CPHA=0).

How l9963t get CPHA information on uC side?

[SRomeo]

Hi Frank,
When L9963T is configured as SPI SLAVE (NSLAVE = 0)
- CLK -> generated by external source
- CPOL/CPOL = not explicitly set (automatically inherited by μ, SPI SW config)

When L9963T is configured as SPI MASTER (NSLAVE = 1)
- CLK -> generated by L9963T
- CPOL = set manually/by pin (JP5)
- CPHA = set manually/by pin (JP3)

So master L9963T configuration is consistent with slave one.

You can also try to monitor L9963T current absorption, checking if supply range fits the "range of functionality"

Anyway, I suggest taking a look to L9963T datasheet to check if you are encountering some edge cases.
https://www.st.com/resource/en/datasheet/l9963t.pdf 

Best regards,
Simone Romeo
AEK Team

[Frank2201]

Measured voltages with oscilloscope, dont see any glitches.

VDD=4.89VDC

VIO=3.33VDC

That would be in green working condition.

Ordered another pair of demo board and see if i received some faulty one.

Meantime I will continue to play.

The weird situation is that when i put 4n7 capacitor on MOSI by uC side, then i receive correct data on other side.

Best regards

Frank

[Frank2201]

One thing im sure of it, L9963T on uC side seems to ignore my setting from encoder side (CPHA=0), only sample data on falling edge clk (CPHA=1).

I changed spi setting in uC:

hspi3.Init.CLKPhase = SPI_PHASE_2EDGE;

And receive correct data on other side with logic analyzer setting CPHA=0.

Seems this work now, i created loop MISO/MOSI at encoder side and i receive same data as i sent it.

[Frank2201]

***, sorry guys and thank you for help.

Seems i missed one important table in datasheet. You cannot configure L9963T at uC side. So you need to configure SPI settings in uC to L9963T requirements.

L9963T configuration (NSLAVE=0) is:

CPOL=0

CPHA=1

You can only configure CPOL and CPHA at remote side (NSLAVE=1).

Best regards

Frank

Wish you happy weekend ;)