STM32 MPUs

Does the ST LINK v2 support STM32MP235F connection?

Failed to set local time on STM32MP257.Firstly, I tried to use the commanddate -s "yyyy-mm-dd xx:xx:xx", and system can successfully return the time I set. But when I again use “date” to get the local time, system still return the wrong time in 2024.Then I tried to write into RTC, but still failed.Now because of the failure of time setting, all the apt command are unavailable.So I want to know how to correctly change the local time and RTC time, or to find an alternate way to apt-get package.Thank you.

I am currently using the distribution version: V5?rt 6.1.82-rt patch?stm32mp257 I am using the TSN mode of the STM32MP257 switch and found that once I set the date, it reverts to the time before the setting after a period of time, and also causes a probabilistic hang during shutdown or reboot. After investigation,this is caused by the deptp service being enabled in the TSN service. My current application only uses the switch mode and does not require TSN. Is it appropriate to disable deptp? What other services can be disabled to enhance system stability?  

This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.I've followed the build instructions for the STM32MP distribution package 6.6.116 and managed to build the boot sd card for MP135F-DK and that works fine.When i build for MP257F-EV1 board, the build works fine and the boot sd card appears ok, but during boot it looks like the kernel load resets the processor partway through : [ 4.201246] m_can_platform 402f0000.can: m_can device registered (irq=76, version=32)[ 4.204152] stm32-cryp 42030000.crypto: will run requests pump with realtime priority[ 4.204774] stm32-pcie 48400000.pcie: IB MEM 0x0080000000..0x00ffffffff -> 0x0080000000[ 4.221546] stm32-pcie 48400000.pcie: iATU: unroll T, 4 ob, 4 ib, align 64K, limit 4G[ 4.255481] stm32-cryp 42030000.crypto: Initialized[ 4.262966] Galcore version 6.4.21.1.1058597NOTICE: CPU: STM32MP257FAI Rev.YNOTICE: Model: STMicroelectronics STM32MP257F-EV1 Eval

STM32CubeIDE   Version: 2.1.1 Build: 28236_20260312_0043 (UTC)   How can I make sense of this ?  TMicroelectronics ST-LINK GDB server. Version 7.13.0 Copyright (c) 2026, STMicroelectronics. All rights reserved. Starting server with the following options: Persistent Mode : Disabled Logging Level : 1 Listen Port Number : 61234 Status Refresh Delay : 15s Verbose Mode : Disabled SWD Debug : Enabled Waiting for debugger connection... Debugger connected Waiting for debugger connection... Debugger connected Waiting for debugger connection... ------------------------------------------------------------------- STM32CubeProgrammer v2.22.0 ------------------------------------------------------------------- Log output file: /tmp/STM32CubeProgrammer_Xj0e11.log Error: Unable to connect to the target device, Access port is not valid. Encountered Error when opening /home/soham/st/stm32cubeide_2.1.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.2.400.2026010

HelloI am building Linux on a custom board using the STM32MP255F-AK.The following error occurs during kernel boot:[ 15.371350] stm32-dwmac 482c0000.eth1: Failed to reset the DMA[ 15.386447] stm32-dwmac 482c0000.eth1 end0: stmmac_hw_setup: DMA engine initialization failed[ 15.389570] stm32-dwmac 482c0000.eth1 end0: __stmmac_open: Hw setup failedAfter embedding printk in the kernel source code to investigate,I found that dwmac4_dma_reset() in /drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c was returning ETIMEDOUT(110).[dwmac4_lib.c]int dwmac4_dma_reset(void __iomem *ioaddr) {u32 value = readl(ioaddr + DMA_BUS_MODE);/* DMA SW reset */value |= DMA_BUS_MODE_SFT_RESET;writel(value, ioaddr + DMA_BUS_MODE);return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,!(value & DMA_BUS_MODE_SFT_RESET),10000, 1000000); }I expect 0x482c0000 to be stored in ioaddr, but different values such as 0x82108000, 0x82128000, and 0x82xxx000 were stored there each time.Ive looked into it from various angles

This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.I wonder how I can enable ETH Clock Output for my Realtek RTL8211F Ethernet PHY. Right now, the crystal for RTL8211F won't start and I don't know why. I'm guessing that it's an unstable crystal. Anyway! To enable the ETH Clock Output for my Ethernet PHY, I've set the the ETH Clock Output:Then I've set the CK_KER_ETH1 to either 25 MHz or 125 MHz. I've chosen the 25 MHz option.According to the STM32MP257F reference manual RM0457, the ETH Clock Output can only be used for 125 MHz.But according to the STM32MPU Wiki, it's possible to use 25 MHz as ETH Clock Output:https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_25_MHz_on_ETH_CLK_-28no_PHY_Crystal-29--CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29-29All you need to do Is to add the pinmuxeth1_clk_pins_mx: eth1_clk_mx-0 {pins {pinmux = <STM32_PI

Board: STM32MP257F-EV1 (also relevant to STM32MP257F-DK)Tool: ST Edge AI Developer Cloud, ST Edge AI Core 2.2.0The "Optimize" step (NBG generation) consistently fails with:"Error while generating optimized file. Generation does not contain any output."Model details:- Architecture: torchvision.models.mobilenet_v2(weights=None, num_classes=100)- Trained from scratch on CIFAR-100 (100 classes), PyTorch 2.5.1+cu121- Input: 3x224x224, output: 100 classes- Quantized on-platform to INT8, per-tensor (per-channel disabled)Attempts (all fail identically):1. Original export, opset_version=122. Simplified via onnx-simplifier (0.4.36) - only reduced redundant Constant nodes (176->108); Conv/Clip/Add/Gemm counts unchanged3. Re-exported with opset_version=174. All used random-value calibration (no .npz calibration dataset provided)No "Show terminal" or detailed log option appears for this specific error on the Optimize step.Control test (works fine):Imported mobilenet_a050_pt_224_qdq_int8_image_cl

Hello,I want to know what is the latest Chromium version supported by OpenST Linux on Scarthgap.Do we have GPU acceleration on it?Thank you in advance,Hiba @PPAGE.13@Billy OWEN @Gregory PLANCHON 

 SetupSTM32MP157, Cortex-A7, bare-metal SDMMC1 → eMMC (61071360 blocks, 512B), CardType 1 Kernel clock: pll4_p_ck (125MHz) via RCC_SDMMC12CKSELR IDMA: single-buffer mode Test: single-block write (512B) to block 4096, then read-back + compare Problem After a cold power-on, the first HAL_MMC_WriteBlocks_DMA() intermittently fails with TX FIFO underrun. Not every cold boot — boot-to-boot random, same config either way.On a boot where it fails, it fails on every retry (tested 5x), even with a full peripheral reset (RCC AHB6 reset + reinit) between each attempt — card info (BlockNbr etc.) verified correct every time, so it's not stale driver/card state.Read never fails, on the same bad boot, same clock, same peripheral.Register data — same board/config, two different cold bootsPassing boot:DCOUNT@DataEnd: 0x0, STA@DataEnd: 0x100 → RESULT: PASSFailing boot (5 attempts, each after full reinit):Attempt 0: DCOUNT@Err=0x098, STA@Err=0x1010, ErrCode=0x10(TXUNDERR)→0x14 (+CMD timeout on stop)Attem

 Hello ST Team,I am working  on the STM32MP257F , using OpenSTLinux 5.0.17 and the ST TSN switch stack v6.I would like to confirm whether the TSN Ethernet switch is officially supported on the STM32MP257F-DK boardNOTE:I understand that the DK board has only one externally accessible Ethernet port and that it can be used as a TSN endpoint. I have enabled the TSN switch, and the following interfaces are available:lowlan0end0sw0p1sw0p2sw0p3sw0epWith the TSN switch enabled, the switch interfaces are created and sw0p1, sw0p2, and sw0p3 are visible. I have connected an external PHY to sw0p3.root@stm32mp2-e3-d2-99:~# ethtool sw0p3Settings for sw0p3:Supported ports: [ TP MII ]Supported link modes: 10baseT/Full100baseT/Full1000baseT/FullSupported pause frame use: NoSupports auto-negotiation: YesSupported FEC modes: Not reportedAdvertised link modes: 10baseT/Full100baseT/Full1000baseT/FullAdvertised pause frame use: NoAdvertised auto-negotiation: YesAdvertised FEC modes: Not reportedLink partner

I would like to gather information on the following points. Kindly guide me on these aspects:Identify the CMOS image sensors supported by the STM32MP255F and STM32MP257F. Determine whether the VB66GY and VB16GZ sensors are compatible with the STM32MP255F and STM32MP257F, including the required driver-level integration and software support.

Hello ST Team,I am working on an AI-based Driver Monitoring System on an STM32MP257F board using an IMX335 MIPI CSI camera, libcamera,GStreamer and STAI-MPU.I am facing a memory allocation / segmentation fault issue when using a custom STAI-MPU application.------------------------------------------------------------HARDWARE------------------------------------------------------------Board:STM32MP257FCamera:Sony IMX335 MIPI CSICamera interface:CSI / DCMIPPDisplay:Weston / WaylandCamera source:LIBCAMERA------------------------------------------------------------SOFTWARE------------------------------------------------------------libcamera:0.3.0+dirtyPython:3.12The exact OpenSTLinux/X-LINUX-AI version and other system information can be provided if required.------------------------------------------------------------KNOWN-GOOD ST APPLICATION------------------------------------------------------------I tested the official ST face-recognition example:https://github.com/STMicroelectronics/meta

Hi:Does I have STM32MP257F-EV1 board and another board can generate BT.656 video source without I2c setting.I want to use DCMIPP parallel interface to get the image. I modify the device tree in stm32mp257f-ev1.dts/ {... clocks { cec_clock: cec-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12000000>; }; dummy_cam_clk: dummy-cam-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <54000000>; }; pad_clk: pad-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <100000000>; }; };...};&dcmipp { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcmipp_parallel_pins_a>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dcmipp_parallel_in: endpoint { remote-endpoint = <&dummy_camera_out>; bus-type = <6>; bus-width = <8>; pclk-sample = <0>; }; }; };};&

Hello Team, On the Development Board, pin PN12 is used to detect whether an SD card is inserted or not; however, it is also required by xspm_p2_ncs, so I don’t think we can simultaneously use XSPIM1, XSPIM2, and PN12. Is there any other pin you would recommend for the purpose of detecting an SD card? Also, I am using the mechanical switch to detect the SD card. In the Datasheet, SDMMC1 is specified for the SD card However, in the AN5967 Document, SDMMC2 is preferred for the SD card. Which port, SDMMC1 OR SDMMC2, is preferred for a microSD card? Thanking you 

Hi everyone,I’m working on a small STM32 project using a piezo buzzer and would like to generate a simple melody from different frequency tones.I can already generate individual tones by changing the timer frequency, but I’m not sure what the best approach is for playing a sequence of notes with different durations.For example, I would like to create a short melody such as:Note A → short duration Note B → short duration Note C → longer duration Pause → short duration RepeatWould it be better to use a timer with PWM and change the frequency for each note, or is there another recommended approach for generating melodies on STM32?I’m mainly looking for guidance on the structure of the code and how to handle the note frequency and duration cleanly.Thanks in advance for any suggestions!

Hi All!I have successfully run ptp4l as a GM role on the 157d-dk1 kit, using NMEA+GPS in as a reference time. I have a specific setup, where NTP is actually disciplining the system clock and the PHC clock is driven from the CLOCK_REALTIME using phc2sys.I wanted to test the PPS output generation on the PG8 pin, so that I can compare incoming PPS with generated PPS, but I can’t make it work.The board version is C03 (no missing solderbridge), Yocto is Kirkstone (kernel 5.15), ptp4l 3.1.1.I have added PG,8,AF11 to kernel’s device tree (in separate inc file):    ethernet0_rgmii_pins_a: ethernet0-rgmii-0 {        pins4 {                pinmux = <STM32_PINMUX('G', 8, AF11)>; /*PPS OUT*/        };   }; Now I can see in gpioinfo output that it is used by kernel but still set as input.Then tried setting period for the PPS through ptp0 (tried different settings):echo “0 0 0 1 0” > /sys/class/ptp/ptp0/period The “clk_summary” shows and in general ptp4l works:          ethptp_k           

I’m trying to add openAmp to a stm32cubemx project (ioc). I add everything (IPCC1, openAMP exc) but when I compile the project[build] [ 5%] Building C object bsp/CMakeFiles/bsp.dir/CM33/OPENAMP/open_amp.c.obj[build] [ 6%] Building C object bsp/CMakeFiles/bsp.dir/CM33/OPENAMP/openamp_log.c.obj[build] [ 8%] Building C object bsp/CMakeFiles/bsp.dir/CM33/Core/Src/stm32mp2xx_it.c.obj[build] In file included from /home/marco/lavori/qmc/software/qmctest-m33/bsp/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/open_amp.h:11,[build] from /home/marco/lavori/qmc/software/qmctest-m33/bsp/CM33/OPENAMP/openamp.h:25,[build] from /home/marco/lavori/qmc/software/qmctest-m33/bsp/CM33/OPENAMP/open_amp.c:21:[build] /home/marco/lavori/qmc/software/qmctest-m33/bsp/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg.h:15:10: fatal error: metal/compiler.h: No such file or directory[build] 15 | #include <metal/compiler.h>[build] |

Hello,I am working with an STM32MP135DAF on a custom board and am trying to boot OpenSTLinux/Yocto from eMMC.My setup is:MPU: STM32MP135DAFCustom hardware/boardCustom Yocto machineSTM32CubeMX used to generate the Device Tree filesOpenSTLinux / YoctoBoot device: MMCImage: `core-image-minimal`I have created a custom machine configuration and integrated the CubeMX-generated Device Tree files into my Yocto build.The Yocto build completes successfully with:  “bitbake core-image-minimal”. The image and flashlayout files are generated successfully.However, when I try to program the board using STM32CubeProgrammer in USB DFU mode, CubeProgrammer reports that it cannot reconnect to the device.I also connected a serial terminal to the debug UART. During the boot/programming sequence, I see:PANIC at PC : 0x2ffe6405Exception mode=0x00000016 at: 0x2ffe6405The relevant CubeMX-generated DTS files, machine `.conf`, and `local.conf` are attached below.Could someone please help me identify what could ca

Is it possible to start the HDMI from U-boot in STM32MP2?I want to see the start up log.

Hi everyone,I am working on the STM32MP257-EVAL board, where my Cortex-M33 application requires both FreeRTOS and OpenAMP middleware to run together.After referring to the STM32CubeMPU packages, I found separate example projects:One for FreeRTOSOne for OpenAMP (running in bare-metal environment)I tried combining both examples into a single application. The FreeRTOS part is working correctly, but OpenAMP hangs during initialization.After debugging, I noticed that libmetal is getting compiled for the generic platform instead of the FreeRTOS platform. To address this, I changed the toolchain configuration from:-DCMAKE_TOOLCHAIN_FILE=cmake/platforms/stm32mp-generic-gcc.cmaketo:-DCMAKE_TOOLCHAIN_FILE=cmake/platforms/stm32mp-freertos-gcc.cmakeHowever, this results in multiple compilation errors. It seems the provided libmetal port may not be fully compatible with the FreeRTOS platform setup.Has anyone successfully integrated FreeRTOS + OpenAMP together on STM32MP257 (M33 core)?Are there any

HiI designed a PCB with an STM32MP157 using a Micron LPDDR3 memory. When I started the layout, I was advised that the memory would be available at least until 2029, so proceeded in good faith. When I came to order prototype samples back in March, I found that there was a Last Time Buy of August 31st this year.The only option that I had was to change the layout to support DDR3L memory, however with the current DRAM supply crisis, I do not have confidence that this generation of device will have sufficient longevity of supply to justify the investment in mass production.My alternative is to jump to an STM32MP2-based board and use DDR4 or LPDDR4 memory which will likely be available for longer but again with the current supply chain situation, these generations could also be obsoleted sooner than anticipated. I already read of DDR5 and LPDDR6 memories coming on stream.Two questions:With regard to the STM32MP1 and STM32MP2 processors, what is ST’s best guidance about which DRAM memory type

Hi, I am trying to design a custom board with a 1 rank dual die 16Gb LPDDR4, AS4C1G16MD4V-046BIN. I have read the design guide AN5489 and DDR config AN5723. From my understanding there is only one chip select pin for each rank, correct? What do I do? Is there a configuration supported by the STM32MP2x processor with 2 chip select in 1 rank?FYI, I am designing a board based on STM32MP235, so supposedly only 1 rank is usable as per the datasheet.

Hi team ST,As we all know, the major DRAM manufacturers have all announced they will stop fabricating the DDR4 die and only LPDDR4 is still in production, in light of this, does STMicroelectronics has an plan to design a new PMIC more focus on the LPDDR4 configuration with less LDOs and smaller package? Given that we don’t need the external termination for DDR anymore with LP DRAM.

Hi!I've found good programs for surfing on the web (Google, wikipedia, MSN, News etc.) and playing Youtube videos in full 1080p HD. No heavy JavaScript is enabled. Those programs requires an update of the extremely light weight GUI library FLTK 1.3.8 to 1.5.x.  Is there anyway I could do that in OpenSTLinux Yocto SDK?  The name of these programs are: - FLTube Youtube Player  - Dillo Web Browser  These are old technologies from late 90's, but they are extremely optimized to run on low, slow and old hardware. Still maintaining by developers.