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nukersson
Associate II
August 30, 2026
Solved

stm32mp257f-dk watchdog OS reset

  • August 30, 2026
  • 2 replies
  • 69 views

Dear ST-Community,

I was able to run QNX8 on stm32mp257f-dk (see it here: https://github.com/KozhinovAlexander/qnx8-bsp-stm32mp257f-dk)
I have following boot-stage setup:

#Opt	Id	Name	Type	IP	Offset	Binary
-	0x01	fsbl-boot	Binary	none	0x0	arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-programmer-usb.stm32
-	0x02	fip-ddr	FIP	none	0x0	fip/fip-stm32mp257f-dk-ddr-opteemin-programmer-usb.bin
-	0x03	fip-boot	FIP	none	0x0	fip/fip-stm32mp257f-dk-opteemin-programmer-usb.bin
P	0x04	fsbla1	Binary	mmc0	0x00004400	arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32
P	0x05	fsbla2	Binary	mmc0	0x00044400	arm-trusted-firmware/tf-a-stm32mp257f-dk-opteemin-sdcard.stm32
PD	0x06	metadata1	FWU_MDATA	mmc0	0x00084400	arm-trusted-firmware/metadata.bin
PD	0x07	metadata2	FWU_MDATA	mmc0	0x000C4400	arm-trusted-firmware/metadata.bin
P	0x08	fip-a	FIP	mmc0	0x00104400	fip/fip-stm32mp257f-dk-opteemin-sdcard.bin
PED	0x09	fip-b	FIP	mmc0	0x00504400	none
PED	0x0A	u-boot-env	ENV	mmc0	0x00904400	none
P	0x10	bootfs	System	mmc0	0x00984400	none
P	0x11	userfs	FileSystem	mmc0	0x080984400	none

All the .bin files are from OpenSTLinux, s.t. I have working U-Boot. I’ve built boot stage within my own yocto-project: https://github.com/KozhinovAlexander/yocto_stm32mp257f_dk

QNX8 itself is booting well and prints necessary messages. So far I see TF-A (optee) is providing a watchdog, which resets my QNX8 OS after around 32 sec. After looking at .dtsi files in the OpenSTLinux Project (u-boot, optee etc.) I see that iwdg1 is the watchdog used. Unfortunately I can’t acces iwdg1 registers by their address mentioned in reference-manual due to possible RISAF protection. I have still not configured RISAF in QNX8 so far.
Here is my boot log for QNX8 on stm32mp257f-dk:
 

Bytes transferred = 352775�Failed to configure FDT PSCI
Enabling EL1 host hypervisor support
MMU: 16-bit ASID 40-bit PA TCR_EL1=00000012b5183519
GICv2: 416 interrupts
GICv2: routing SPIs to gic cpu 0
cpu0: MPIDR=0000000080000000
cpu0: MIDR=411fd040 Cortex-A35 r1p0
cpu0: DCZID_EL0=0x00000004 (64 bytes)
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 32K linesz=64 set/way=256/2
cpu0: L1 Dcache 32K linesz=64 set/way=128/4
cpu0: L2 Unified 512K linesz=64 set/way=1024/8
cpu0: GICv2 cpu interface 0
Loading IFS...done
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
cpu1: MPIDR=0000000080000001
cpu1: MIDR=411fd040 Cortex-A35 r1p0
cpu1: DCZID_EL0=0x00000004 (64 bytes)
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 32K linesz=64 set/way=256/2
cpu1: L1 Dcache 32K linesz=64 set/way=128/4
cpu1: L2 Unified 512K linesz=64 set/way=1024/8
cpu1: GICv2 cpu interface 1

System page at phys:000000009001e000 user:ffffff8040207000 kern:ffffff8040204000
Starting next program at vffffff806008cc80
syspage::hypinfo::flags=0x00000001
No #1262888 WA needed for CPU0
No #1262888 WA needed for CPU1

Welcome to QNX 8.0.0 on STM32MP257F-DK_Board_(MB1605_Var1.0_Rev.C-01) !

Starting WatchDog ...
Starting serial driver (/dev/ser10)
Starting SPI driver
Starting SDMMC driver (/dev/sd0)
Starting shell ...
ksh: No controlling tty (open /dev/tty: No such device or address)
ksh: warning: won't have full job control

There are still some missed drivers, but it is fine so far.
After around 32 sec. I am getting following reset reason from optee and u-boot bootin afterwards:
 

# E/TC:1   Panic 'Watchdog' at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r3/core/drivers/stm32_iwdg.c:218 <stm32_i>
E/TC:1   TEE load address @ 0x82000000
E/TC:1   Call stack:
E/TC:1    0x82006f94
E/TC:1    0x82033bfc
E/TC:1    0x820152fc
E/TC:1    0x820332b8
E/TC:1    0x8200d088
I/TC: Halting CPU 0
NOTICE:  CPU: STM32MP257FAK Rev.Y
NOTICE:  Model: STMicroelectronics STM32MP257F-DK Discovery Board
NOTICE:  Board: MB1605 Var1.0 Rev.C-01
NOTICE:  Reset reason: IWDG system reset (iwdgX_out_rst) (0x2134)
INFO:    PMIC2 version = 0x11
INFO:    PMIC2 product ID = 0x20
INFO:    FCONF: Reading TB_FW firmware configuration file from: 0xe011000
INFO:    FCONF: Reading firmware configuration information for: stm32mp_io
INFO:    FCONF: Reading firmware configuration information for: stm32mp_fuse
INFO:    Using SDMMC
INFO:      Instance 1
INFO:    Boot used partition fsbl1
NOTICE:  BL2: v2.10-stm32mp2-r2.0(debug):lts-v2.10.24-dirty(a07367a1)
NOTICE:  BL2: Built : 16:16:36, Oct  3 2025
INFO:    BL2: Loading image id 26
INFO:    Loading image id=26 at address 0xe041000
INFO:    Image id=26 loaded: 0xe041000 - 0xe049650
INFO:    BL2: Doing platform setup
INFO:    RAM: LPDDR4 1x32Gbits 1x32bits 1200MHz
INFO:    Memory size = 0x100000000 (4096 MB)
INFO:    BL2: Loading image id 1
INFO:    Loading image id=1 at address 0xe000000
INFO:    Image id=1 loaded: 0xe000000 - 0xe000326
INFO:    FCONF: Reading FW_CONFIG firmware configuration file from: 0xe000000
INFO:    FCONF: Reading firmware configuration information for: dyn_cfg
INFO:    FCONF: Reading firmware configuration information for: risaf_config
INFO:    RISAF2: No configuration in DT, use default
INFO:    BL31 max size = 0x17000 (94208B)
INFO:    BL2: Loading image id 3
INFO:    Loading image id=3 at address 0xe000000
INFO:    Image id=3 loaded: 0xe000000 - 0xe0169f0
INFO:    BL2: Loading image id 19
INFO:    Loading image id=19 at address 0x81fc0000
INFO:    Image id=19 loaded: 0x81fc0000 - 0x81fc3958
INFO:    BL2: Loading image id 4
INFO:    Loading image id=4 at address 0x82000000
INFO:    Image id=4 loaded: 0x82000000 - 0x8200001c
INFO:    OPTEE ep=0x82000000
INFO:    OPTEE header info:
INFO:          magic=0x4554504f
INFO:          version=0x2
INFO:          arch=0x1
INFO:          flags=0x0
INFO:          nb_images=0x1
INFO:    BL2: Loading image id 8
INFO:    Loading image id=8 at address 0x82000000
INFO:    Image id=8 loaded: 0x82000000 - 0x82086058
INFO:    BL2: Loading image id 2
INFO:    Loading image id=2 at address 0x84400000
INFO:    Image id=2 loaded: 0x84400000 - 0x8441d488
INFO:    BL2: Loading image id 5
INFO:    Loading image id=5 at address 0x84000000
INFO:    Image id=5 loaded: 0x84000000 - 0x841c53b0
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0xe000000
INFO:    SPSR = 0x3cd
INFO:    ARM GICv2 driver initialized
NOTICE:  BL31: v2.10-stm32mp2-r2.0(debug):lts-v2.10.24-dirty(a07367a1)
NOTICE:  BL31: Built : 16:16:36, Oct  3 2025
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
I/TC: Early console on UART#2
I/TC: 
I/TC: Embedded DTB found
I/TC: OP-TEE version: 4.0.0-dev (gcc version 13.4.0 (GCC)) #1 Fri Oct 20 18:29:31 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: WARNING: All debug access are allowed
I/TC: Override the OTP 124: 0 to 0x18db6
I/TC: WARNING: Embeds insecure stm32mp_provisioning driver
I/TC: PMIC STPMIC REFID:2.@ V1.1
I/TC: Platform stm32mp2: flavor PLATFORM_FLAVOR - DT stm32mp257f-dk.dts
I/TC: OP-TEE ST profile: system_services
[    0.000000] SCP-firmware 2.13.0-intree-optee-os-4.0.0-dev
[    0.000000] 
[    0.000000] [FWK] Module initialization complete!
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x84000000
INFO:    SPSR = 0x3c9
I/TC: Reserved shared memory is disabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are enabled


U-Boot 2023.10-stm32mp-r3 (Oct 02 2023 - 14:39:59 +0000)

CPU: STM32MP257FAK Rev.Y
Model: STMicroelectronics STM32MP257F-DK Discovery Board
Board: stm32mp2 (st,stm32mp257f-dk)
Board: MB1605 Var1.0 Rev.C-01
DRAM:  4 GiB
optee optee: OP-TEE: revision 4.0 (2a5b1d12)
I/TC: Reserved shared memory is disabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are enabled
Core:  420 devices, 42 uclasses, devicetree: board
WDT:   Started watchdog with servicing every 1000ms (32s timeout)
NAND:  0 MiB
MMC:   STM32 SD/MMC: 0, STM32 SD/MMC: 1
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:   eth0: eth1@482c0000
No EFI system partition
No EFI system partition
Failed to persist EFI variables
Hit any key to stop autoboot:  0 
Boot over mmc0!
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:8...
119359 bytes read in 212 ms (549.8 KiB/s)
BootOrder not defined
EFI boot manager: Cannot load any image
STM32MP>

 

My questions are so far:

  1. Did I found it correctly - optee uses iwdg1 as a reset watchdog?
  2. How do I access watchdog kick/ping/reset from OS (Linux, QNX8)? Do I need RISAF for it?
  3. Would it be possible to point at watchdog driver in OpenSTLinux, which is intended to feed reset wathcdog (iwdg1?) configured within OPTEE?

    Kind Regards,
    Alexander
Best answer by Erwan SZYMANSKI

Hello ​@nukersson,
First of all, thank you for this work sharing and congrats for this QNX portage on STM32MP257F-DK board.

1- Yes correct, OP-TEE configures the IWDG1 and expects to be kicked by the upper layer software part, that is Linux in the standard OpenSTLinux ecosystem, and QNX in yours.

2- RISAF is only managed by the secure side (OP-TEE) and there is no driver required at Kernel level. The configuration we set by default in our examples should be enough to set everything right.

3- In Linux, to kick OP-TEE watchdog, we pass through a common ARM driver called drivers/watchdog/arm_smc_wdt.c to make a SMC call to OP-TEE that is configured to know that he is supposed to ping its configured watchdog (here IWDG1). We do not write directly from Linux in IWDG1 registers because IWDG1 is configured as a secure IP, and so reachable only by OP-TEE. This is so up to OP-TEE to first, configure IWDG1, then kick IWDG1 driver. Kernel stack should make the request to OP-TEE to kick it. More information here: https://wiki.st.com/stm32mpu/wiki/IWDG_internal_peripheral (more particularly you can check the chapter called Software frameworks and drivers to see drivers used in each boot stage).

Kind regards,
​​​​​​​Erwan.

2 replies

Erwan SZYMANSKI
Erwan SZYMANSKIBest answer
ST Technical Moderator
August 31, 2026

Hello ​@nukersson,
First of all, thank you for this work sharing and congrats for this QNX portage on STM32MP257F-DK board.

1- Yes correct, OP-TEE configures the IWDG1 and expects to be kicked by the upper layer software part, that is Linux in the standard OpenSTLinux ecosystem, and QNX in yours.

2- RISAF is only managed by the secure side (OP-TEE) and there is no driver required at Kernel level. The configuration we set by default in our examples should be enough to set everything right.

3- In Linux, to kick OP-TEE watchdog, we pass through a common ARM driver called drivers/watchdog/arm_smc_wdt.c to make a SMC call to OP-TEE that is configured to know that he is supposed to ping its configured watchdog (here IWDG1). We do not write directly from Linux in IWDG1 registers because IWDG1 is configured as a secure IP, and so reachable only by OP-TEE. This is so up to OP-TEE to first, configure IWDG1, then kick IWDG1 driver. Kernel stack should make the request to OP-TEE to kick it. More information here: https://wiki.st.com/stm32mpu/wiki/IWDG_internal_peripheral (more particularly you can check the chapter called Software frameworks and drivers to see drivers used in each boot stage).

Kind regards,
​​​​​​​Erwan.

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    nukerssonAuthor
    Associate II
    September 2, 2026

    ​@Erwan SZYMANSKI Thank you for your support. The tipp for SMC call was the right one. QNX8 defines already psci_call function, s.t. I was able to utilize it for watchdog stop and reset functionality like it done here: https://github.com/KozhinovAlexander/qnx8-bsp-stm32mp257f-dk/blob/main/bsp/qnx800.bsp.hw.st_stm32mp257f-dk/bsp/BSP_st-stm32mp257f-dk_be-800/src/hardware/startup/boards/stm32mp2/stm32mp2_wdt.c

    Interestingly only both mentioned functions worked - other SMC calls provided in the enum generated OPTEE exceptions. I think the problem could be in the psci_call implementation. But for now it is fine.

    Current implementation does not have wdtkick implemented still, therefore there the watchdog was just disabled by startup programm. Otherwise the MVP QNX8 on stm32mp2 is functional. Still there is a lot of missin stuff :)

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