STM32 MCUs Embedded software

In the STM32CubeF0 pack, PWR/PWR_CurrentConsumption example for Nucleo-F030R8:void SleepMode_Measure(void){ GPIO_InitTypeDef GPIO_InitStruct; /* Configure all GPIO as analog to reduce current consumption on non used IOs */ /* Enable GPIOs clock */ /* Warning : Reconfiguring all GPIO will close the connection with the debugger */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // <<< Here! GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pin = GPIO_PIN_All; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);void StopMode_Measure(void){ GPIO_InitTypeDef GPIO_InitStruct; /* Configure all GPIO as anal

​@User_MV Thank you for all this information and for the CMake files. This helped me to create an OEMiRoT project exclusively with CMake, dropping the need for any provisioning script. ​@Saket_Om I’m looking forward for the possibility of using MCUBoot middleware directly in STM32CubeMX2. We can download it from the “Pack manager”, but it explicitely says “No” in the “Compatible” column (and thus it is not present in the middleware section). So what I did was just a git submodule, using mcuboot’s hal2 branch. A change that I needed to do : increase the memory buffer length of mcuboot, otherwise I was getting errors with MBEDTLS_ERR_MPI_ALLOC_FAILED return code, with an user application of size 0x16000. So I doubled the value of ROT_MBEDTLS_MEM_BUF_LEN, from 0x1000 to 0x2000. As a side note for anyone, make sure to call HAL_RCC_Reset() in either the OEMiRoT, or the user application. ST does it in the user application, but I prefer the other to do it in the OEMiRoT - just before jumping

I'm facing a very strange issue on my custom hardware based on the STM32N6 when trying to run my application using the Run configuration in STM32CubeIDE. My setup consists of a secure-only application with an FSBL and a separate application. The project is generated with STM32CubeMX, built in STM32CubeIDE, and uses TouchGFX. The build completes successfully. Debugging the application works perfectly, and I don't encounter any issues. However, as soon as I try to launch the exact same application using the Run configuration, it stops working. Both the Run and Debug configurations use the same build and the same ".launch" settings. The behavior is as follows: 1. I power-cycle the board while it is in development mode.2. I start the application using the Run configuration.3. The application does not produce any output on the display.4. After a few seconds, the watchdog expires, the board resets, and it ends up in a boot failure state. Interestingly, if I instead: 1. Power-cycle the board.

I use H563 and G491 MCUs. There is HAL_ADCEx_Calibration_Start() on both MCUs to calibrate for single or differential ended inputs. If I have mixed single and differential ended inputs on the same ADC, which do I use? Single or differential?

Struggling with a really weird issue here. I'm working on a project using Zephyr on an STM32U5A5ZJT6Q. We are using an LSE-clocked LPTIM as the tick source, PM enabled with STOP0 and STOP1 modes.At some point, we started noticing random crashes, which seemed to occur sporadically, more often on some boards than others. These would usually be in the `idle` zephyr thread, specifically after a `wfi` instruction. Digging around, I found some errata (specifically 2.2.26 for STM32U575xx STM32U585xx, related to flash prefetch, and now also 2.2.6 for STM32U59xxx STM32U5Axxx, related to wake-up from stop mode). HardFault on wake-up from Stop mode may occur in debug modeDescriptionA HardFault may occur at wake-up from Stop mode when the following conditions are met:• Device is in debug mode.• DBG_STOP bit is set in DBGMCU_CR.• A wake-up event/interrupt from an SRD peripheral (except EXTI) occurs in a timing window of four clockcycles during Stop mode entry sequence. SRD peripherals are

Hiya.I’m currently trying to capture an image from the OV7670 camera module over DCMI + GPDMA. I’ve been able to capture images, but I’ve run into an odd issue with vertical blanking. Using the STM32U575RIT3. I have the module configured for RGB565 in QVGA and I can fully confirm that it is outputting what it is meant to, the issue is just with GPDMA and getting it into memory.In GPDMA=Standard Request, I only get ¾ of the image, with the first ¼ being blanked. Sample image in GPDMA Standard RequestIn Linked List mode, I can only seem to get up to ½ of the image. I get ¼ with a single node, ½ with two nodes, but no more when introducing more nodes.Sample image in GPDMA Linked List ModeI can confirm that the GPDMA_CxDAR register shows that it has indexed by an entire image and reached the FrameEvent callback in StandardRequest Mode. In LinkedList mode, it seems to just lost the second half of the image as I do not get the callback and the DAR register records an increment of half the im

The FDCAN_RxHeaderTypeDef typedef (for the STM32G4) includes:uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. Acceptance of non-matching frames may be enabled via HAL_FDCAN_ConfigGlobalFilter(). This parameter takes 0 if the frame matched an Rx filter or 1 if it did not match any Rx filter */From the code, this member is loaded with the ANMF bit of an RX FIFO element. The documentation for this shows that ANMF is an abbreviation for “Accepted non-matching frame” - so the comment is correct (‘1’ → did not match a filter). Which means the member name should be something like ‘IsNotFilterMatchingFrame’.Code completion within CubeIDE does not show the comment:which means it is easy to get the state wrong if the name is interpreted semantically!Probably not a lot that can be d

Hi experts:    I’m working on NUCLEO-G031K8 trying to use its I2C2(I2C1 is OK),I set PA11/PA12 as SCL/SDA, pull-up, OD, when I tried to read data, I found SCL is always high, but SDA has datas, I can’t figure out what’s missing, can you help me with that?Bill 

I’m trying to have my own TCP Client with NetXDuo that I can configure with CubeMX in VSCode for the Nucleo-N6.There is an NetXDuo Echo Client example project in N6 FW1.3.0 and 1.2.0 releases. The 1.2.0 version of the sample has no IOC but works in VSCode, the 1.3.0 version has the IOC file but doesn’t work in VSCode.I’ve additionally started from CubeMX and generated a fresh project with the matching configuration from the sample project and attempted both a static IP and DHCP (this works with the sample code) but can’t get either functionality to work.Is there an IOC version of a TCP client with NextXDuo somewhere that is based on CMake that I can integrate into VSCode that has proven to work with either a static IP and DHCP? I have searched countless times and I can’t find any.

On the H743 using V1.12.1 library, CubeIDE,  the USB_CoreReset() procedure occasionally fails to reset the Host USB core in debug mode.  I have added a reset call which seems to fix the issue in debug, reproduced below.I would like to know if this is a known issue in CubeIDE debug mode?See fix below in USB_CoreReset() // mod - added extra reset as in debug the USB host core fails to reset correctly at timesstatic void USB_Hard_Reset(USB_OTG_GlobalTypeDef *USBx){/* Example from USBH_LL_Init() in usbh_conf.c USB_HOST/Target/__HAL_RCC_USB_OTG_HS_FORCE_RESET();HAL_Delay(50);__HAL_RCC_USB_OTG_HS_RELEASE_RESET();HAL_Delay(50);/* --- FS BACK-POWER FIX START ---HAL_PWREx_EnableUSBVoltageDetector();uint32_t to = 100000;while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY) == 0U && to--) ;assert(to > 0);*/uint32_t timeout;/* 1. Mask all interrupts and stop AHB transactions */USBx->GINTMSK = 0U;USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; // disable global int/* 2. Wait for AHB idle */time

Hello,I am making a device which will play encoded audio files from a (Q)SPI flash and I wanted to use the STM32C55 (with its internal DAC). Alas, I haven’t been able to find flash/RAM/CPU frequency requirements for the codecs except for MP3 Helix (https://github.com/liuduanfei/helix), but I would rather use Opus because it has a better bitrate-to-quality ratio.Does anyone have experience with decoding audio on the STM32C55 (or any similar MCU for that matter)? How much flash and RAM was needed for the decoder?Thanks.

I am experiencing a critical issue with the hardware video encoder (VENC) on the STM32N6 when processing low-light frames.Setup: Sensor: IMX335 connected to STM32N6 Capture Pipeline: DCMIPP configured in 1080p@15FPS capturing and writing to RAM in RGB565 format. Encoder Input: The same RGB565 buffers are passed to the VENC. Storage: The encoded H.264 stream is saved directly to an SD card. The Problem:When the camera enters a dark environment (very low-light conditions) and I manually reduce the Gain/Exposure to very low values (where the image should be almost completely black), the video recorded on the SD card starts to progressively brighten up until it becomes completely white (a "flashbang" effect).When playing back the file on a PC, the transition from black to fully white takes about 1-2 seconds (accumulating over several frames).Key Observations & What I've Already Tested: DCMIPP Output is OK: I have a live preview on an LCD screen displaying the input buffers direct

Dear STM Support Team,We are currently developing a rear-view camera application on the STM32N6570 platform. Our existing implementation was developed using the Sony IMX335 image sensor, and we are now planning to migrate the design to a custom board using the OmniVision OV2312 sensor.We would like to clarify the following: Does the existing STM32N6570 camera driver framework support the OV2312 sensor directly? If not, is there an official OV2312 sensor driver available from ST? Can the existing IMX335 driver be adapted for OV2312, or is a separate sensor-specific driver required? If an OV2312 driver is already available, could you please provide the driver package, reference code, or the relevant documentation for integration with the STM32N6570 imaging pipeline? Your clarification will help us proceed with the custom hardware integration and software development.Thank you for your support, and we look forward to your response.

Hello,I am using an STM32L431 as an I2C Slave and an RL78/G13 as an I2C Master.I am trying to transmit data from the STM32L431 (Slave) to the Renesas RL78 (Master).When the RL78 performs an I2C read operation, the following callback sequence is observed on the STM32: 1 HAL_I2C_AddrCallback(Direction = Read) 2 HAL_I2C_ErrorCallback(ErrorCode = 4) 3 HAL_I2C_ListenCpltCallback()Inside the AddrCallback I start the transmission using: HAL_I2C_Slave_Seq_Transmit_IT(hi2c, tx_buffer, tx_length, I2C_FIRST_AND_LAST_FRAME);The function returns HAL_OK.The transmit buffer contains a simple incrementing pattern, length 20 byte: 01 02 03 04 05The STM32 reports that transmission has completed: XferSize = 20 XferCount = 0However, immediately afterwards the ErrorCallback is called with: TextErrorCode = 4According to stm32l4xx_hal_i2c.h this corresponds to: HAL_I2C_ERROR_AF (Acknowledge failure / NACK).On the RL78 side, the receive buffer does not contain the transmitted data. Expected: 01 02 03 04 05 ..

Hi there !I have a quick question about where the data are save. If i create one const array [1024] the data inside the array (because i write the word const in front) are save inside the falsh ? and this give to me more space in the ram  right ? and is the same if i create one struct and i acces with pointer ?  and please some one can help me and show where i can find all this kind of information like book tutorial website youtube ectThank you Sergio

My problem: my SPI2 module doesn’t appear to be clocking in data even if it is configured a full duplex master.Context:I am developing the firmware on a board that some other team designed and they picked PB13 (SCK), PB14 (MISO) and PB15 (MOSI) to implement SPI2.  I am aware of the fact that those pins are shared with the UCPD dead battery detection feature and that:Dead battery detection must be disabled Clock rate of SPI is limited to ~3MBdI am developing my drivers bare-metal (no LL or HAL), but since I couldn’t figure out how to make this work, I decided to try with the HAL code generated by STM32CubeMX.I created a new project on that software with software package v1.7.0 which appears to be the latest at this time.I simply configured the clock tree to use HSI (64MHz) → /2 → PLL1 (M=4, N=24, Q=4) = 48MHz.  I then use SPI2 prescaler to get 1.5Mbd out of PLL1Q (I tried lower data rate too).  The SPI module is configured in full duplex.  Here is the main function code after HAL initia

Dear Community, I’m struggling to find a way to prevent SMDCube IDE code generation to overwrite a changed #define. I’ve tried the usual wrapping with /* USER CODE BEGIN …   with no result, and also try to dig online for some similar issue, but no luck.Any hint on how I can actually make this work? Details:STM32U595STM32CubeIDE Version: 1.19.0 specific define ( in STM32U5xx_HAL_CONF )#define USE_HAL_ADC_REGISTER_CALLBACKS 1U /* ADC register callback disabled */this one is overwritten each time code generation is run from the graphic GUI Goal is to have ADC complete callback registrable to multiple functions. When I force the above define to 1, all works as expected, but when I have to run code generation then the define is rolled back to the standard “0U”, which obviously is not desirable.Tried also to override the define from outside the file, but this creates a neverending chain of errors. Best Regards,Anton 

 I am working with an STM32F0 device and I want to implement a firmware update mechanism.My current plan is to split the internal flash into three regions:Bootloader: 0x08000000Application Slot 1 (App1): 0x08004000Application Slot 2 (App2): 0x08008000The bootloader always runs first.Only one application slot is active at a time.The update flow is planned as follows:If App1 is currently running and a new firmware update arrives, the new firmware is written to App2.If App2 is running, the new firmware is written to App1.After the update, the bootloader selects which slot to boot.My concern is about the linker script (.ld) configuration:When I build a new application firmware, I set the flash origin address in the linker script to:  FLASH (rx) : ORIGIN = 0x08004000This works correctly when the firmware is programmed into App1.However, if the same binary is written to App2 at address 0x08008000, the vector table, reset handler, and absolute addresses inside the firmware will

Hello,I downloaded STM32CubeN6-main FW 1.4.0 from GitHub and am trying to build the Nx_WebServer FSBL example.  I am getting this error message:11:26:53 **** Build of configuration Debug for project Nx_WebServer_FSBL ****make -j16 all make: *** No rule to make target 'C:/STM_FW/STM32CubeN6-main/Middlewares/ST/threadx/common/src/tx_block_pool_performance_info_get.c', needed by 'Middlewares/threadx/Performance/tx_block_pool_performance_info_get.o'. Stop."make -j16 all" terminated with exit code 2. Build might be incomplete.11:26:55 Build Failed. 1 errors, 0 warnings. (took 2s.214ms)I don’t see any source code at the C:\STM_FW\STM32CubeN6-main\Middlewares\ST\threadx location, is there another project I need to build first?

I’ve been trying to adapt the code from the STM32WB5MM-DK QSPI_ReadWrite_IT example to a Renesas part. However, I have not been able to get it into Quad mode. For this part I need to write 0x02 into register 0x31 as I understand the data sheet.From monitoring the status register I can see that the write enable bit gets set and cleared, but the QE (quad enable) bit doesn’t get set.Also, in reviewing the code for the DK, I don’t see code to set the quad enable bit as per the Infineon S25FL128S data sheet.In searching the support forums, I see references to a routine called QSPI_QuadEnable, but I have not been able to find corresponding code.I’m obviously missing something. Can someone point me in the right direction - either specific to this board or a more generic solution?Thanks

Hello, everyone on the forum.I'm building a system using the STM32H735G-DK, ThreadX, and NetX Duo.I'm writing logs to a microSD card to keep a record of the system's operation.I integrated FTP into the system so that log files can be downloaded via Ethernet.Since the FTP download speed is only about 150 kilobytes per second, it takes a long time to download large log files.Currently, `nx_ftp_server_create` allocates an 8K-byte stack for the FTP server. What are some ways to increase FTP download speeds?I would appreciate any advice. 

I used STM32F103 in a mix configuration of bare-metal&HAL supplied by STM32CubeMX. I'm not sure ST can provide the documentation that can be referenced to generate the SBOM for cybersecurity purpose. Is there any recommended tool to scan the firmware project folder. If ST is yet to provide a way to auto-generate SBOM for cybersecurity requirement, possible to use manually curated SPDX-based JSON format for machine processing. If anyone had gone through similar process for regulatory review, can you please share the experience? Any inputs/advise would be greatly appreciated. Thank you.

Setup  - MCU: STM32U595VITxQ (Cortex-M33)  - ADC: ADC4, 57Mhz，12-bit, 7 channels, 6400 Hz sample rate, triggered by TIM1  - Data path: GPDMA1 in linked-list circular mode, double-buffered with half/complete callbacks (128 samples per half-buffer). DMA writes directly into a static INT16U s_adc4_result[256][7] buffer in normal SRAM.  - Signal chain: external current/voltage sensors → signal conditioning board (op-amps, anti-alias filter, DC bias) → ADC4 input pins  - Firmware: FreeRTOS, half-callback copies 128 samples per channel into a ring buffer (PF_TOTAL_WAVE_NUM = 40 slots × 128 samples), pf_task consumes from queue  Symptom  Most of time, everything works fine. But some times something wrong happened，in a log file we captured, channels simultaneously read byte-identical constant values.Questions:  1. Has anyone seen an STM32U5 ADC report "healthy" (no OVR, no error, ADSTART set) while consistently delivering a constant code per channel? Are there silicon errata I should check?  2

Hi everyone,I'm working on an STM32H743-based product that already has a custom bootloader and I'm looking for the best industry practice for implementing a bootloader fallback mechanism.Current architecture0x08000000 Primary Bootloader0x08020000 Factory Application0x08080000 Default ApplicationThe bootloader already performs:Application validity checks (MSP and Reset Handler) CRC verification of the Factory and Default applications UART firmware update Automatic fallback from Default Application to Factory ApplicationThe applications are working as expected.New requirementThe new requirement is that if the primary bootloader becomes corrupted, the system should be able to boot from a backup bootloader stored elsewhere in flash, without requiring physical access (the device is remotely deployed).I understand that after reset the Cortex-M7 hardware simply does:MSP = *(0x08000000)PC = *(0x08000004)and immediately jumps to the Reset_Handler.My understanding is:If the vector table or R

Dear STM32 Technical Team:Our original design is implemented on the STM32F407, utilizing a single ADC pin for analog signal acquisition. Upon detection of a key trigger signal, high-speed data acquisition is performed via TIM1-triggered ADC1 with DMA transmission, where Analog Watchdog 1 is configured with Threshold A for boundary supervision. In the idle state without a key trigger, TIM2-triggered ADC2 operates in background mode with Analog Watchdog 2 (Threshold B) to continuously monitor abnormal signal fluctuations in real time.Due to the limited on-chip RAM of the STM32F407, we have migrated the firmware to the STM32L4S5 microcontroller. However, this device only features a single ADC peripheral, which prevents the independent dual-ADC operation implemented in the original design. Furthermore, although the STM32L4S5 integrates three analog watchdogs, the hardware does not support configuration of independent threshold levels for separate operational modes.We kindly request your of