STM32 MCUs

I have an STM32H7 project (created by TouchGFX) that uses FreeRTOS.FreeRTOS uses the systick, so the HAL uses TIM2 for it's timebase.However, HAL_IncTick is never called, so calls to HAL_Delay never return.HAL_InitTick() is being called during startup and this results in TIM2 counting and its update interrupt flag being set. However, the interrupt handler never gets called.

New programmer and new to the STM32 ecosystem as well.I am working with a STM32F401 as it has 5v tolerant inputs and 2 32bit clocks.I have a simple program that reads the 2 32bit TIMs (2&5) in encoder mode, sums the results and then outputs a quadrature signal to a device. I have the GPIO outputs set to "low" speed, which according to my reading should give them a max of 2Mhz output.Even this appears to be too fast with the HCLK set to the maximum of 84Mhz. On a scope the signal looks pretty bad and my device (cheap DRO) cannot read the signal at that speed. If I drop the HCLK down to 4Mhz everything works as expected and I get real nice square waves on the scope but this feels "kludgy"My question is, is there something else I should be looking at to adjust the output rate? HAL_Delay etc feel even more kludgy than stepping the clock down.Any help would be greatly appreciated; Code follows while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ int32_t cnt1 = __HAL_

HI, I'm using stm32h7s78-dk, and setup the external flash following this tutorial The "appli" project is in external flash and runs with no issue. Now I want to write some config data such as display brightness to the external flash according to user input but I can't find a way to do that. I tried HAL_FLASH_Program(), but it seems can only modify the internal flash. Then I tried to enable EXTMEM_MANAGER_APPLI in CubeMX to use EXTMEM_WriteInMappedMode(). However, I can't reinitialize the xspi in "appli" project..What is the appropriate way to do this? Any input is much appreciated!

Hello,I need to build a USB headset(mic+speaker) using STM32H742VIT6 for a project. I want the stm32h7 to be recognized as a audio device when connected to a PC/android device. Is this possible?This is my first time using a STM Board with cubeMX and cubeIDE, so I want to build the microphone part first. I am having trouble programming the board, specially what middleware to use, how the structure of the project works in the ide, what would be the setup e.g. clock config, dma, adc, timer configuration. It would be nice if I could get some resources/guide on how to start, because I am lost inside the mx and ide!Hardware: WeAct Studion STM32H742VIT6MAX4466 mic

Hi everyone,My company recently purchased a new ST-Link/v2 programmer. The problem is that after the firmware update, the device stopped working, and when I press the Connect button on the STM32CubeProgrammer, the following error appears:Error: ST-LINK error (DEV_USB_COMM_ERR)I tried using an ST-Link/V2 programmer I bought a few months ago, and everything works fine (I only replaced the programmer, same USB cable, same programming cable).The programmer is original, I'm sure of it. I purchased the programmer from DigiKey.Even the serial number I see appears to be genuine. When I try to update the firmware, I get the following result:Can anyone help me solve my problem?Thanks  

PART NO: STM32H743IIT6CUBE_IDE VER: 1.19.0SDK : STM32Cube FW_H7 V1.12.1LSE PART NO. : CM9V-T1A-32.768kHz-12.5pF-20PPM-TA-QCHello everyone,I am trying to use RTC on mentioned STM part number. I have enable LSE and configured the RTC.Currently i am not using any battery, i am using a power supply with 3V to VBAT.After boot up inside HAL_RCC_OscConfig, i am getting timeout while checking RCC_FLAG_LSERDY flag.   while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } }   The sequence is, once i have provided VDD then VBAT, everything works fine.Next i just turn off the VDD, VBAT is still present.Then i turn on the VDD and facing this issue.Another thing to note is, i am not facing this issue with LSI. So i changed the crystal but facing the same issue.Also the PDR_ON pin is connected to VDD according to specifications.Is it possible to provide any insight of why this is happe

Hi! I am trying to muddle my way through a design that revolves around an STM32U5 MCU, and am specifically trying to think about ESD protection. I have been referencing AN5612, which quite helpfully provides lots of specific examples for various applications (though it seems to perhaps be falling out of date, as a handful of the devices mentioned seem to now be marked NRND). One thing that I can't quite wrap my head around, though, is ESD protection as it relates to running some or all of the power domains of the MCU at 1.8V. For example, the datasheet for the stm32u59xx has an Absolute Maximum Ratings table that shows most FT (5V tolerant) pins have a max rating of either 5.5V or min(Vxx+4.0, 6) - so 5.8V in this case - with other pins having a max rating of 4.0. I know these are DC voltages, but I think I understand that it's these values I should use when trying to parametrically search for ESD protective devices, such that they have forward voltages above 1.8V and clamping vol

Hello,first let me start this post by mentioning that I'm still very much a beginner.I'm writing my own abstraction layer functions for the N657X0.While running my clock_config() function, I ran into an issue that I don't know how to fix. The function works as follows:- reset RCC->CR, CRGR1, CFGR2- enable MSI and wait for MSI ready bit- set CPU & SYS clock source to MSI and wait for clock source confirmation bits- disable all other oscillators and all PLL- reset RCC->HSICFGR- configure HSI- enable HSI and wait for HSI ready bit- set CPU & SYS clock source to HSI and wait for clock source confirmation bits- disable MSI- reset RCC->MSICFGR- configure MSI- enable/disable oscillators (if HSIEN=0 then MSIEN=1 and vice-versa)- reset RCC->ICxCFGR- configure ICx- reset RCC->PLLxCFGRx- configure PLLx- enable PLLx and wait for PLLx lock ready bit- check CPU and SYS clock source selection- check if source is actually active by checking the corresponding ready bit again- sel

Hello, I'm trying to use TouchGFX. I created a new project and clicked on Generate code. Afterwards I get the following error message, which I do not know how to handle. Do you have any suggestions?Generate CodeCopy FrameworkCopying TouchGFX framework version 4.24.1 to C:\temp\testgfx\MyApplication\touchgfxDoneGenerateWrote config/gcc/app.mkWrote config/msvs/Application.propsWrote generated/gui_generated/include/gui_generated/common/FrontendApplicationBase.hppWrote generated/gui_generated/include/gui_generated/common/FrontendHeapBase.hppWrote generated/gui_generated/include/gui_generated/common/SimConstants.hppWrote generated/gui_generated/include/gui_generated/screen1_screen/Screen1ViewBase.hppWrote generated/gui_generated/src/common/FrontendApplicationBase.cppWrote generated/gui_generated/src/screen1_screen/Screen1ViewBase.cppWrote generated/simulator/gcc/MakefileWrote generated/simulator/include/simulator/mainBase.hppWrote generated/simulator/include/simulator/video/D

Hi, I'm a bit stuck.   I'm trying to program watermarks for BANK2 (to make the entire bank secure so I can read the whole area using secure alias) for a custom boot-loader.   The code below is executing in secure context from BANK1 (and no bank swap).  It runs without error, but after a reset, the option bytes are still unchanged.   Im calling it with (FLASH_BANK_2, 0, 63, 0) as arguments. (63 being the last flash page of a 512KB bank - device is 1MB)   I am pretty sure I misunderstand something.   Kind Regards, Nick /**  * @brief Configures or Disables Secure Watermark for a specific bank.  * @PArambank: FLASH_BANK_1 or FLASH_BANK_2  * @PAramstart_page: Start page (Set > end_page to disable)  * @PAramend_page: End page  * @PAramlaunch: If SET, triggers a System Reset immediately to apply changes.  * @return true if the operation was successful, false otherwise  * @note to disable WM, set start_page > end_

Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at input indicates that the receiver is ready to receive)DEPOL = 0 (0 at output indicates that data is valid)DERDYCFG = 0b11 (Both PSSI_RDY and PSSI_DE alternate functions enabled)EDM = 0b00 (Interface captures 8-bit data on every parallel data clock)Chip STM32H7R3Z8T6, clocked at 600MHz from HSI, placed at PCB, powered by 3.3VPSSI kernel clocked by 150MHz and 300MHz (PLL from HSI)Transmitted data is rising numbers from 0 to 15, stored in array in AHBSRAM1, manualy written by core to PSSI->DR as 32bit values (four data bytes at one write). See source code:while (1){ if(PSSI->SR & PSSI_SR_RTT4B){ // wait until space in PSSI buffer PSSI->DR = arr[idxx]; // place data to buffer idxx++; // index to next data if(idxx >= BLOCK_SIZE

Hello,I designed a custom PCB using the STM32F401RE (LQFP64), but I cannot connect to the MCU through SWD. I am using an ST-Link probe and the st-probe command-line tool.When I run the probe command, the ST-Link probe itself is detected, but the target MCU is not properly identified. The tool reports the flash size as 0x00.MCU: STM32F401REDebugger: ST-Link probeTool: st-probeObserved behavior:ST-Link probe is detected correctly.The MCU is not detected.Flash size reported as 0x00.Power measurements:VDD = 3.3 VVDDA = 3.3 V (through ferrite bead BLM18AG601SN1D)VCAP ≈ 1.2 V (2.2 µF capacitor connected directly, ~8 mm trace, no vias)NRST = 3.3 VTotal board current ≈ 18 mA (two LEDs also present)The MCU does not heat up, and current consumption appears normal.Power architecture:12 V input → buck converter → 5 V → LDO → 3.3 V (MCU supply)Analog supply filtering:VDD → ferrite bead → VDDADecoupling capacitors are placed near the MCU.Debug connections:SWDIO → PA13SWCLK → PA14NRST connected to th

We are developing a STiROT/OEMuROT bootloader for a customer using the above chip. This is based on the STM32H7S78-DK sample. The customer has developed the main application and have added support to download a new firmware image over Ethernet. This image is stored in external RAM and once downloaded an md5 checksum of the image is stored and a flag is set to indicate that new firmware is available. At this point the device is restarted to switch to the bootloader. We've added code to the bootloader that checks if a new firmware image is available in external RAM. If a new image is available the bootloader validates that the image is OK by recalculating the md5 checksum. The validation passes and at this point a section in external FLASH is erased. After the erase completes, the image in external RAM is copied into the external FLASH and the copied image is validated via md5 checksum - which fails. On further investigation it is the data being read from external RAM that is incorrect (

In OEMiROT_Boot/Src/low_level_ext_flash.c, function Ext_Flash_EraseSector(),  a call is made to EXTMEM_MemoryMappedMode() immediately before the sector erase takes place, to temporarily disable memory-mapped mode for the external flash, with the function called again afterwards to re-enable it.As @ken5 reported previously, we found that these flash erases can cause corruption in the external RAM.After a lot of experimentation and head-scratching, we've found that if the external RAM is also removed from the memory map before a flash erase, and re-enabled afterwards, these corruption issues appears to go away (pending further testing).I'm guessing that this wasn't spotted in ST's testing because OEMiROT doesn't use the external RAM until later (if at all), so any corruption doesn't matter. However, our adapted OEMiROT does use the external RAM, and the data corruption was a serious problem.(Incidentally, we saw occasional corruption in the external fla

I am using STM32h757xih6 Controller Ethernet pinging data transfer issue came by using lwip and udp protocol getting hard fault handler (polling method) 

Hello, I am experiencing a problem with ADC1 and ADC2. I configured them in Dual Regular Simultaneous Mode, where ADC1 acts as the master and ADC2 acts as the slave. The ADC channel connections are as follows: ADC1 Channel 1: 24V_Sense ADC1 Channel 2: 5V_Sense ADC2 Channel 14: IOut_Sense ADC2 Channel Vrefint: Internal reference voltage However, I noticed that IOut_Sense always has a value, while 24V_Sense is unstable and fluctuating. OUTPUT:V24:24011 mV | V5:3 mV | I:23653 mA V24:8807 mV | V5:3 mV | I:8675 mA V24:8726 mV | V5:1 mV | I:8675 mA V24:8844 mV | V5:3 mV | I:8675 mA V24:23767 mV | V5:1 mV | I:23528 mA V24:23853 mV | V5:0 mV | I:23590 mA V24:23727 mV | V5:0 mV | I:23435 mA V24:23968 mV | V5:0 mV | I:23481 mA V24:8832 mV | V5:3 mV | I:8675 mA V24:23541 mV | V5:0 mV | I:23388 mA uint32_t adc_dual_buffer[4]; int main(void) { HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_ADC1_Init(); MX_ADC2_Init(); MX_USART1_UART_Init(); MX_I2C1_Init();

Hi,I powered the NUCLEO-F410RB board externally by changing the JP5 jumper to select the E5V power supply and applied 5 V to the E5V pin. Initially, I did not have an external ST-LINK, so I switched JP5 to U5V and programmed the Nucleo board through USB.During this back-and-forth process, I powered both internally and externally at a time. After this, the board started consuming more current, and U1 in the NUCLEO-F410RB schematic overheated. Eventually, the VOUT and GND pins were found to be shorted.   After troubleshooting, I found that the short was inside the on-board debugger IC (ST-LINK), between VDD and VSS, so I removed the debugger IC.Later, I purchased an external ST-LINK and tried to program the Nucleo board again. I powered the board externally with 5 V on E5V. The main MCU is getting 3.3 V, but there is almost no current consumption, whereas earlier it used to draw around 200–700 mA.For debugging, I removed the CN2 jumpers and made the following connections:C

I'm trying to set up FSMC in muxed mode to read_write external NOR flash devices. Muxed pins goes through 2 8-bit latches 74HC574D.The problem is that currently i can barely read from external NOR and it's not accepting commands.Firstly HAL_NOR_Init(&hnor1, &Timing, NULL) returns HALL_ERR  since it fails to read CommandSet from NOR. It should read address 0x13 from CFI and get 0x02 or 0x01 as a result, but write commad makes no effect and as a result driver reads at 0x13 from memopry start.After analyzing what's going on on the FSMC bus I still cand fing any clues. Here is an example how it performs ReadID sequence, using standard HAL_NOR_ReadID Everything looks correct, 3 sequences 0x555 - >0xAA, 0x2AA -> 0x55 and 0x555 -> 0x90, but reading 0x00 and 0x01 right after returns data from NOR not the deviceID I've also tried bitbang mode with same pins and code below successfully reads deviceID. So after all it's not a witing problem, but maby timings or so

Hi Together,I am currently trying to use the FMAC hardware accelerator. Normal usage already works. Now for numerical stability I want to implement the filter as second order sections (sos). According to RM0481:Cascaded filters must either be combined into a single stage, or implemented asseparate filters. In the latter case, multiple sets of filter coefficients can be pre-loadedinto the memory, one set per stage, and only the X2_BASE address changed to selectwhich set is used.To do this I currently:Concatenate all the stage coeffs into one vector:static int16_t const b_Coeffs_0[b_Coeff_len_0] = { 55, 111, 55 }; static int16_t const a_Coeffs_0[a_Coeff_len_0] = { -3745, -258 }; static int16_t const b_Coeffs_1[b_Coeff_len_1] = { 16384, 32767, 16384 }; ...static int16_t all_coeffs[sos_Coeff_Count] = { b_Coeffs_0[0], b_Coeffs_0[1], b_Coeffs_0[2], a_Coeffs_0[0], ...On setup input the vector as b coefficients:filter_Config.Clip = FMAC_CLIP_ENABLED; filter_Config.Filter = FMAC_FUNC_IIR_DIRECT

Hello ST,1. ds14258 Rev.6 Table 57 on p.163 specifies a positive I_inj of "N/A" for pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2 (as opposed to a positive I_inj of "0 mA" in the row above for pins PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2) Does "N/A" mean that it is *impossible* to cause any positive injection (on pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2) with pin voltages between 0V and 4V when VDD is unpowered or at 0V?i.e. Do pins other than PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2 have some kind of "nice" input structure that allows powering them when VDD is unpowered or at 0V?  2. ds14258 Rev.6 states in Note 3 on p.128: "Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value." Does "not possible" in the above sentence mean:a. that externally raising the voltage on those pins to between 0V and 4V when VDD is unpowe

TouchGFX adds a redundant line ending to .cproject file when clicking generate code even if nothing has changed.This causes changes to show up in git and also makes merging and pull requests more complicated.In STM32CubeIDE the line ending is removed after making any change to the project (and optionally reverting the change). -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> +<?fileVersion 4.0.0?> +<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> I'm using TouchGFX 4.23.2, but the problem was also present in older versions. Using STM32CubeIDE 1.15.1, but older version had the same effect.Please fix this.  

The image sensor inputs a 24 MHz clock and outputs a 40 MHz clock, and the captured image size is 1280×1024×2. When the trigger mode of the image sensor is enabled, the main loop execution speed slows down by approximately 1.6 seconds; when the trigger mode is disabled, the system operates normally. Furthermore, I intend to transmit the images collected by DCMI via USB, but these two modules cannot be enabled simultaneously. Additionally, when the DCMI is operating, serial port interrupts will cause abnormal operation of the DCMI. How should I resolve this issue? Below is the configuration code and main loop code of my STM32H743:

  I found more issues. 1. Missing SRAMEN bit in RCC_AHBENR register. I think it is bit 9. See STM32U0 RM0503 page 54, RCC_AHBSMENR register and STM32F0 RM0091. With this new bit, reset value is: 0x0000 0300Also I think that it is missing SRAMRST bit in RCC_AHBRSTR register. It should be bit 9. This problem is also on STM32G0 and STM32C0 RMs. 2. Missing TIMx_OR2 and TIMx_OR3 registers mentioned on RM0503 page 553.This problem is also on STM32G0 RM0444 and RM0454, and STM32C0 RM0490. 3. STM32F0 RM0091 didn't mention how internal break input (called "Internal break event sources") is selected. See pages 359 and 514. STM32F0 RM0091 doesn't have an equivalent to STM32U0 RM0503 figure 164 on page 592. 4. STM32U0 RM0503 pages 107, 108 and 118, mentions pin PE6 but it doesn't exist in datasheet. RTC_TAMP3/TAMP_IN3 is pin PB15 and not pin PE6. From STM32U0 DS:TAMP_IN1 PC13TAMP_IN2 PA0TAMP_IN3 PB15TAMP_IN4 PC5TAMP_IN5 PA1 5. STM32U0 RM0503 page 413: Missing description of VREFBUF_CCR regist

Is there any alternative of "B-CAMS-OMV" to use with "STM32F746G-DISCOVERY" as in my region it is not available and the cost will be huge if I want to ship it to Bangladesh. So, is there any alternative modules that I can search for?

I can't get the STLink drivers installed on Windows 10 / 11 aarch64 Parallels VM running on Mac M1.Is there any support for ARM64 Windows STLink drivers?