Solved

SummaryOn my STEVAL-VL53L9, the VL53L9CX boots, installs FW patch 0.17, reaches STREAMING with all error bits clear — and then faults on the very first frame. The reference SPAD array reports zero amplitude on every channel, as if the VCSELs never fire.I have reproduced this with two different VL53L9CX parts and three independent host implementations, each of which is known to work on another STEVAL-VL53L9. I have run out of things I can change from software, and I would like to understand what the firmware error codes mean.SetupBoard: STEVAL-VL53L9, VL53L9CX hand-soldered by me Host: ESP32 (DevKit v1) through the J2 header, plain I2C at 400 kHz, address 0x29 Clock: on-board 12 MHz Y1 (R25 removed, R24 fitted, R23 removed); EXT_CLOCK = 12000000 J3 (Host IO) = 3.3 V; VDDA_CFG = 2.8 V, VDDIO_CFG = 1.8 V XSHUT driven by the host, SYNC_IN tied high, INTR not used (FRAME_READY polled) FW patch 0.17 (9,865 bytes, byte-identical to vl53l9_patch.h in STSW-IMG053 / 53L9A1 BSP)SymptomDefault pro

Hello,I’ve run into what appears to be a documentation error or a H/W bug with the GPDMA on the STM32U585. I’ve set up a 512-byte circular DMA buffer with HT and TC interrupts to capture UART Rx data.  I’ve also enbaled DTE and SUSP interupts because I want to handle UART IDLE detection. In the UART IRQ handler (caused by IDLE), I suspend the DMA channel.  The DMA IRQ handler then triggers on SUSPF and I grab the current BNDT value, update an internal index, and then resume the DMA.  The DMA continues until the block is complete (TC), then reloads only the CxDAR from memory (only UDA set in CLLR update bits).  According to documentation, the BNDT value should be reloaded from an internal value stored when the channel was enabled.  This works as expected until the TC after suspend/resume event.  After a suspend/resume, the BNDT appears to reload a different value, and continues to use that new value. The only work around I found was to add UB1 to the CLLR update bit fields and provide a

On STM32H733, the HAL provides __HAL_DBGMCU_FREEZE_FDCAN() in stm32h7xx_hal.h but it is conditionally compiled:#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))#endifDBGMCU_APB1HFZ1_DBG_FDCAN is not defined in stm32h733xx.h, so the macro does not exist at compile time and calling it gives:error: implicit declaration of function '__HAL_DBGMCU_FREEZE_FDCAN'Questions:Is FDCAN freeze during debug halt supported on STM32H733? If yes, why is DBGMCU_APB1HFZ1_DBG_FDCAN missing from stm32h733xx.h — is this a bug in the device header? What is the correct bit position to use as a workaround via direct register write? I need to pause the FDCAN peripheral during debugging, that is my goal. Thanks you very much for helping me out. 

I configured ADC1 to be triggered by TIM2_CH2 and TIM2 compare channel 2 on STM32F429 with CubeMX, and enabled their interrupt, TIM2 CC2 ISR was run but ADC EOC ISR not run. I tested both by LED and by debug in CubeIDE, both results were the same. When debug in CubeIDE, after TIM2 CC2 ISR was run, STRT=0 and EOC=0 in ADC1 SR, which indicated that ADC1 was not triggered. However, if I configured ADC1 to be triggered by TIM2_TRGO and TIM2 trigger output from Update event, ADC1 was triggered.My settings in CubeMX:CubeMX and CubeIDE project files:

IssueI am working on an iOS application that uses the ST25SDK for NFC operations.The ST25SDK documentation indicates that the iOS SDK is based on J2ObjC 2.4. I downloaded the J2ObjC 2.4 source and attempted to build it locally on an Apple Silicon Mac.However, I am currently unable to complete the J2ObjC 2.4 build. I have also tested J2ObjC 3.1, which builds successfully in the same environment.QuestionCould you please confirm whether J2ObjC 3.1 is supported/compatible with the ST25SDK iOS version I am using, or whether the application must specifically use J2ObjC 2.4?In particular, I would like to clarify: Is J2ObjC 2.4 a strict requirement for the ST25SDK iOS Objective-C sources? Can J2ObjC 3.1 be used as a drop-in replacement if it successfully builds? If J2ObjC 3.1 is not compatible, are there any required patches or source changes that would allow the ST25SDK to work with J2ObjC 3.1? Is there an official/prebuilt J2ObjC 2.4 distribution recommended for the current ST25SDK, so

Hi ST expert,I am developing a 3P4W Smart power meter C&I class, we are planning to design a multi-rate data sampling! S1 for power metrology by dedicated metering IC ADE9000, S2 for feature-stream acquisition NILM inference at 4 kHz continues sampling rate by internal ADC of STM32H755 and S3 for transient capture at 20kHz triggered capture by ADS131M08. Communication that STM32H775 would handle including Wi-Fi, RS485, 100Mbit ETH, SD card 32GB(eMMC optional) status LED x3 and USB-C for programming and debugging. We also have AI model to build into the MCU for edge inference, time series model! I not sure if STM32H755 series can handle all this tasks or not. Could you please help me evaluate this platform for my design? Additional info, please let me know. Thank you.

Hello Team,We have manufactured 500 boards using STM32WBA52CGU6. During testing, we tested 50 boards, out of which 5 boards are not advertising BLE, while the remaining 45 boards are working normally.We have attached the schematic and PCB layout screenshots for your reference.Our PCB is a 2-layer board, and we have not followed a controlled 50 Ω impedance for the RF trace. Could this be contributing to the BLE advertising issue on these 5 boards?Could you please review the attached schematic and layout and help us debug this issue? We would also appreciate your guidance on the key parameters or measurements we should checkon the failed boards compared with the working boards.

Hi ST Community,I am designing a custom board with STM32WLE5CCU6 (UFQFPN48 package) for a LoRa application in the 470–510 MHz band.I will use RFO_LP only, with +14 dBm output power and VDD_MCU = 3.3 V.Could you please provide the ZOPT (optimal impedance) for the PA output matching network at 475 MHz for this configuration?AN5457 Appendix A only covers 868/900/915/923 MHz, so I cannot find the data for 475 MHz. If there is any reference design or application note for this frequency, please point me to it.Thank you very much.

The name of the variable in the Live Expression in dark mode is wrong It should be white instead it’s blackVersion: 2.2.0Build: 29186_20260626_0934 (UTC)

Hi, I find the startup file generated by CubeMX2 for my STM32C551xx MCU doing something weird that I couldn’t understand. /**  * @brief  This function is the Reset Handler called on controller reset.  * @param  None  * @retval None  */__WEAK __NO_RETURN void Reset_Handler(void){  __set_PSP((uint32_t)(&__INITIAL_SP));  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));  SystemInit();         /* CMSIS System Initialization */  __PROGRAM_START();    /* Enter PreMain (C library entry point) */}The code shown above reset the PSP pointer rather than MSP. I’m not sure if I do some misunderstanding about the stack pointer, as PM0264 indicated that MSP should be the one reset to the value retrieved by the reset handler. 

In the STM32CubeIDE project generated by STM32CubeMX for the default configuration on STM32F429I-DISC1 board, I can not find any reference to TIM1 except in the init function, i.e. ITM1 is initialized but not start. What TIM1 is used for?

Greetings,I have finished the schematics of my custom STM32MP13X based PCB, My aim with this PCB is to learn high speed digital circuit design & how the board bring up is done & various other things like loading RAM's timing information from an EEPROM to initialize RAM, etc.I would appreciate if my schematics could be reviewed & any potential issues could be pointed out before I start my PCB design (or worse, produce the PCBs) because I’m a student who’s funding this project from my part time job & I really don’t want to make an expensive mistake.The schematics are majorly based on STM32MP135-DK's reference schematics (MB1635) & I have attached the schematics (PDF) along with BoM file for package size information, etc.I would also like to mention that the schematics have been designed to keep costs low, This is also why most of the components will be sourced via LCSC & This is also why there’s no eMMC on-board. I also omitted the termination resistors on DDR bec

Hi all, i have very simple gpio pushbutton debounce code, but 50% of the time it still gets a double-bounce (led toggles twice), i.e. the debounceCount is double incremented as the interrupt service routine is mysteriously called twice. How can this be if the interrupt is immediately disabled?.  Is the switch bounce sometimes so quick that two presses are queued up before the interrupt is disabled?Within main() , if the button is pressed, there is a while(1) if(butIsPressed) {butIsPressed=FALSE; HAL_Delay(1000); and then HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);}void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin){HAL_NVIC_DisableIRQ(EXTI4_15_IRQn);debounceCount++;HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_3); // Toggle The Output (LED) PinbutIsPressed = TRUE;} 

In the RM0090 manual, for the OTG_HS, the MPSIZ field definition is the same for all enpoints: Note: this is not the case for OTG_FS where endpoint 0 has a specific format for field MPSIZ. However, the code in file stm32f4xx_ll_usb.c sets this field to 0 in order to set the maximum packet size to 64 byte.See lines 1355 and 1356: /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;It is OK with the OFG_FS definition on DIEPCTL0_MPSIZ but not with the OTG_HS definition.My question is: what should be done here:setting 0 in MPSIZ, like the code does or setting 64 in MPSIZ as specified in the RM0090 documentation?

I have a board which is in the STM32V8 family but i cant find anything about its datasheet or anything to work on it how can i work on a board which has no data sheet or any pin out things , even if i create a file using stmcubeide i cant find its ioc file for that particular project 

Hi, I have just installed STM32 Cube IDE 2.0.0 for Mac OS Apple Silicon, and then installed the GCC ARM for STM32 10.3-2021.10 toolchain through the toolchain manager. However when I import a project using this toolchain I get the nullgcc error.I also tried creating a new project and setting the toolchain to 10.3-2021.10 but still get the same error.When I look into the eclipse plugins folder searching for the toolchain binaries, I only see a .jar file but not the actual compiler folder with the binaries ls -l /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/ | grep gnu-tools-for-stm32Jul  9 11:22 com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10_1.2.100.202508251041.jarJun 26 11:52 com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.macosaarch64_1.0.0.202602081740un 26 11:52 com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1_1.0.100.202601091506.jarJun 26 11:52 com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32_2.

I have been trying to use the motor profiler to characterize a motor that I do not have full specs for. I am getting “firmware is not a profiler fw….” which took me down the Application Configuration road in the MC workbench. There I discovered that the Profiler check box did not exist. That led me to the Current Sensing configuration section where the following is displayed:Current Mode is off and grayed-out Current Reading Selected hardware boards do not support this featureThe EVLSPIN32G0A2 of course, is a 3 shunt board. I am running 6.4.2 of the MC workbench. So what is happening here? I’m fairly new to this toolchain and thinking there’s a work-around someplace. For a little more context, I am trying to run a 6-step model with a Hall-sensored motor. I can get things to run in Pilot but there’s wonky stuff going on with the GUI. Thinking some of these observations may be related to the current sensing topo as well?

Title: ST67W611M1A6BTR – Are BOOT and UART required when using the factory firmware without modification?Hello,I am designing a custom board using an STM32G474 as the host MCU and an ST67W611M1A6BTR as the Wi-Fi/Bluetooth network coprocessor.I intend to use the standard X-CUBE-ST67W61 software and communicate with the module through the SPI/AT interface. I do not intend to develop or debug custom firmware running inside the QCC743 SoC.After reviewing the ST67W611M1 datasheet, the B2413 reference schematic, AN6316, and the ST hardware setup wiki, I would like to clarify the required programming and debug connections.In the B2413 schematic, module pins 1 to 4 are shown as: Pin 1: JTMS Pin 2: JTCK Pin 3: BOOT_WW6 / JTDO Pin 4: JTDI However, in the ST67W611M1 datasheet, pins 1, 2, and 4 are marked as RESERVED and are required to be left unconnected for the A6B/A6U variants.My questions are as follows: Does every production ST67W611M1A6BTR module contain a usable mission firmware imag

Stm32cubeAI studio output      -------------------------------------------------------------------                       STM32CubeProgrammer v2.23.0                        -------------------------------------------------------------------ST-LINK SN  : 0042001A3234510337333934ST-LINK FW  : V3J17M10Board       : NUCLEO-N657X0-QVoltage     : 3.30VSWD freq    : 8000 KHzConnect mode: Under ResetReset mode  : Hardware resetDevice ID   : 0x486Revision ID : Rev ZDevice name : STM32N6xxDevice type : MCUDevice CPU  : Cortex-M55BL Version  : --Opening and parsing file: NUCLEO-N657X0-Q_Appli.elfMemory Programming ...  File          : NUCLEO-N657X0-Q_Appli.elf  Size          : 2.60 MB   Address       : 0x34000000Erasing memory corresponding to segment 0:Erasing memory corresponding to segment 1:Erasing external memory sectors [16 57]Error: failed to erase memoryError: failed to erase memoryRun failed: Error: STM32CubeProgrammer exited with code 1 

From the documentation it sounds like the STM32WB vectors to the reset hander when it exits STANDBY and lower power modes, correct? 

Hi,Does anyone know if there is a list of the operating systems supported on the Cortex-A35 cores of the STM32MP257 ? Any information or pointers would be welcome.Thanks!

STM32MP257F-EV1: SPI3 Slave Mode — NSS Pin (PB1) Fails to Claim Despite Correct ConfigurationSummaryOn the STM32MP257F-EV1 evaluation board, configuring SPI3 in slave mode (spi-slave;) works correctly for the SCK, MOSI, and MISO signals, but the NSS (chip select) pin — PB1, using the documented-correct AF1 alternate function — silently fails to be claimed by the pin controller. No error or warning is logged anywhere. All three other SPI3 pins on the same bus, using the same AF1 value, claim successfully.HardwareBoard: STM32MP257F-EV1 (MB1936) MPU: STM32MP257FAI3 OpenSTLinux version: 5.0.15-openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18 Kernel: Linux 6.6.116-stm32mp-r3What we are trying to doConfigure SPI3 as an SPI slave (spi-slave; device tree property) so the STM32MP2 can receive data from an external SPI master over the same bus/pins already used for a sensor (previously configured as SPI master).Configuration usedCustom pinctrl group (added to stm32mp25-pinctrl.dtsi):spi3_slave_pins

Subject: X-NUCLEO-CCA02M2 PDM-over-SPI capture issue on STM32MP257F-EV1 - discontinuous clocking suspectedHello ST Support Team,I'm working with an X-NUCLEO-CCA02M2 dual PDM microphone expansion board interfaced to an STM32MP257F-EV1 evaluation board, and I'm running into a data-quality issue I'd appreciate your guidance on.Setup:- X-NUCLEO-CCA02M2 board, using onboard microphone M2 (MIC_PDM34_OB), routed via SB10 solder bridge to CN10 pin 15- Connected to the STM32MP257F-EV1's SPI8 peripheral in Linux userspace via /dev/spidev, MISO on mikroBUS pin 5 (PZ1), clock supplied from SPI8's own SCK (mikroBUS pin 4, PZ2) to CN10 pin 29 (MIC_CLK_NUCLEO)- Power from CN6 pin 3 (3.3V), GND from CN6 pins 6/7- Capturing via repeated SPI read calls (spidev, bufsiz increased to 65536, Mode 0)Issue:Short, isolated SPI captures (around 2000 bytes at a time, with pauses between reads) show clearly responsive behavior - bit density in the captured stream increases noticeably when speaking near the microp

Where can I find STM32H5F5J-DK demonstration firmware full source code?

Hi,On STM32U575CGU3, I see a reproducible +200 µA increase in current after calling MX_ADC1_Init() once. Even after HAL_ADC_DeInit(), ADC reset, and disabling VddA, the additional current does not return to the original baseline.Here is the minimal code:cint main(void){ HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_GPDMA1_Init(); MX_ADC1_Init(); // +200uA increase MX_OCTOSPI1_Init(); MX_SPI1_Init(); MX_USB_OTG_FS_PCD_Init(); MX_USART1_UART_Init(); MX_ICACHE_Init(); // ADC Disable HAL_ADC_DeInit(&hadc1); __HAL_RCC_ADC1_FORCE_RESET(); __HAL_RCC_ADC1_RELEASE_RESET(); HAL_PWREx_DisableVddA(); while (1) { __NOP(); }}Questions Has anyone observed similar behavior on U5 devices (ADC bias or VREFBUF staying active after initialization)? Are there known conditions where ADC/VREFBUF analog blocks remain powered even after DeInit and VddA OFF? Any hints on additional steps required to fully shut down the analog domai