STM32U575CGU3: Does ADC_Init leave analog bias active? Looking for others who observed similar current increase

[k.morohoshi]

Hi,

On STM32U575CGU3, I see a reproducible +200 µA increase in current after calling MX_ADC1_Init() once. Even after HAL_ADC_DeInit(), ADC reset, and disabling VddA, the additional current does not return to the original baseline.

Here is the minimal code:

c

int main(void)
{
    HAL_Init();
    SystemClock_Config();

    MX_GPIO_Init();
    MX_GPDMA1_Init();
    MX_ADC1_Init();         // +200uA increase
    MX_OCTOSPI1_Init();
    MX_SPI1_Init();
    MX_USB_OTG_FS_PCD_Init();
    MX_USART1_UART_Init();
    MX_ICACHE_Init();

    // ADC Disable
    HAL_ADC_DeInit(&hadc1);
    __HAL_RCC_ADC1_FORCE_RESET();
    __HAL_RCC_ADC1_RELEASE_RESET();
    HAL_PWREx_DisableVddA();

    while (1) {
        __NOP();
    }
}

Questions

• Has anyone observed similar behavior on U5 devices (ADC bias or VREFBUF staying active after initialization)?

• Are there known conditions where ADC/VREFBUF analog blocks remain powered even after DeInit and VddA OFF?

• Any hints on additional steps required to fully shut down the analog domain?

Thanks.

[KDJEM.1]

Hello ​@k.morohoshi ;

 

 Can you check and share which ADC kernel clock source STM32CubeMX generated for ADC on your project?

I recommend you to use HCLK clock source.

 

Thank you.

Kaouthar

[k.morohoshi]

Thank you for the suggestion. I checked the ADC kernel clock source generated by STM32CubeMX, and it was originally set to HSI. After changing the ADC kernel clock to HCLK as recommended, the additional current (~200 µA) disappeared.

So the issue was caused by the ADC kernel clock selection. With HCLK as the kernel clock, the analog domain shuts down correctly and the current returns to the expected baseline.

Additional observation: Before switching to HCLK, calling HAL_ADC_DeInit(), forcing ADC reset, and disabling VddA did not reduce the current. It seems that once MX_ADC1_Init() is executed, some analog bias remains active in RUN mode when the ADC kernel clock is HSI. After switching to HCLK, STOP2 also works correctly and the current drops to the expected low‑power level.

This may help others who observe similar behavior on U5 devices.

Thanks again for the support.