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I require urgent technical support regarding a VIPer22A-based dual output power supply design (5V/800mA and 12V/200mA).I have designed and manufactured the transformer according to my calculations; however, the power supply is not operating properly. I have attached the following documents for your review:Schematic PCB Layout Transformer Design DataI would appreciate it if you could review the attached files and provide your feedback and recommendations as soon as possible, as this matter is highly urgent and is currently affecting our development schedule.Thank you in advance for your support. I look forward to your prompt respons

Dear ST team,I have configured the ST87M01 for sending +CEREG URCs when registration state changes with AT+CEREG=5.But the modem attaches, but does not sent +CEREG notification (see traces below): Is this a nominal behavior ?AT+CEREG=5OKAT+CEREG=?+CEREG: (0,1,2,3,4,5)OKAT+CEREG?+CEREG: 5,2,"","",,,,"",""OK+CEREG: 0,"","",,,,"",""+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CEREG: 0,"","",,,,"",""+CSCON: 0+CEREG: 2,"","",,,,"",""+CSCON: 1+CSCON: 0+CEREG: 0,"","",,,,"",""#STENG: ECID=08507721,SRV1=FFB11868,PLMN=0002F802,EDRX=00000001,PSM=00000000,ENRG=000045D7#SLEEP DRX 2.4s#WAKEUP DRX#STENG: ECID=08507721,SRV1=FFB21868,PLMN=0002F802,EDRX=00000001,PSM=00000000,ENRG=00000016#SLEEP DRX 1.7s#WAKEUP DRX Best regards,Thierry

Hello,I'm currently integrating the SBSFU 2.8 for one of our board, that use a STM32H753, with a dual-slot configuration.I'm adapting the example for the STM32H753ZI. For now, this mostly involves modifying the USART (use the 6 instead of the 3).I am currently trying to set up the system to resume operation after a power outage. I defined ENABLE_IMAGE_STATE_HANDLING in the projects SeCoreBin and SBSFU.This is my scenario:Download of a UserAppValidation of the downloaded UserAppDecryption of the UserAppStart of the swap between the DownloadSlot and the ActiveSlot/!\ Power outage!Power returnResume of the installation processCurrently, the resume always fails when checking the trailer (in CheckTrailerMagic).I checked what he wrote as trailer (in WriteTrailerHeader), and what is written is indeed what is read after the reset.What's strange is how he slices up what he's checking.If we look at the names of the arrays in the CheckTrailerMagic function, we have:FieldValue readm

Hi, I face the problem with the touchgfx frame rate render has drop periodic after 1000ms that make the animation image (wait circle) has choppiness.My project run on custom STM32U5 has 3MB RAM and 4MB FLASH (I don’t use the external memory). The LTDC configuration at 60Hz(24.5Mhz) for screen 800x480 resolution. The signal when screen not update(full)The signal when screen not update(full)The signal when screen not update(zoom in to see the VSYNC signal)The signal when screen not update(zoom in to see the VSYNC signal) The signal when screen animation the imageThe signal when screen animation the imageThe VSYNC signal is perfect at all.You can run the LogicSystemTimingAnalysis.html in .zip then load the .csv file to see the signal. Thanks,Phat 

Hi, Is there a way to disable Boot0 on PA11 on STM32WL33 ? I can’t find any Bytes Option. The only thing I can find, is we can re map PA11 to another pin.Thanks

Hi all,I am bringing up an ISSI IS66WVO8M8DBLL OctalSPI PSRAM (OctaRAM) on an STM32H563VIT6 overOCTOSPI1 in memory-mapped mode (window at 0x90000000). Reads, register access, and"write a location then read it back immediately" all work perfectly. But any SUSTAINEDor SCATTERED write workload corrupts data: rows that are not continuously re-writtenlose their contents within a few seconds, and some writes come back wrong.This matches errata ES0565 section 2.5.12 ("Variable latency is not supported when arefresh collision occurs during a write access to some OctaRAM memories"). I applied thedocumented workaround - forcing FIXED latency in the memory's configuration register -and I run in the documented MTYP=0b011 (Macronix OctaRAM) mode. The corruption persists,byte-for-byte identical, with the workaround correctly applied and verified by read-back.I have reproduced this on TWO separate boards with identical results, so it is not asingle bad device.Has anyone got OCTOSPI memory-mapped WRIT

STP80NF55-06 MARKING is not same datasheet.Product show marking : P80NF55@ 

 Hello,I have inherited some code where a 5kHz 50% PWM is output in center aligned mode using TIM1. CK_PSC is 275MHz, CK_CNT is 137.5MHz (I think) because PSC = 1.The pattern output matches the implementation:  The yellow trace is a GPIO pin that is toggled in the ISR HAL_TIM_PeriodElapsedCallback(). I want to to keep the same 50% duty but half the frequency to 2.5kHz using the prescaler.From the TRM, it seems I just have to modify PSC from 1 to 2. However, when I do this by poking the SFR register using the debugger, I get the following output:  As you can see, the PWM ratio changes but the frequency does not. I’m at a loss to understand why. So would be grateful for any suggestions.Thank you. In case it helps, here’s my register dump. I have no idea what DMAR is that is my next step.  

Hi everyone,I'm working on an STM32 project where UART communication uses DMA for receiving data. The application works correctly after startup, but after running for a few minutes, the UART stops receiving data intermittently.Project details: MCU: STM32F407VG STM32CubeIDE 1.16 HAL drivers UART2 configured with DMA in Normal Mode FreeRTOS enabled I've already tried: Increasing the DMA buffer size. Lowering the baud rate from 115200 to 57600. Verifying the UART wiring. Checking for overrun errors. The DMA interrupt still occurs, but the receive callback is not always executed.Has anyone experienced a similar issue? Is there a recommended way to keep UART DMA reception running continuously?SolutionThe issue was related to how DMA reception was configured.The following changes resolved the problem: Configure the DMA channel in Circular Mode if continuous reception is required. Restart DMA reception inside the HAL_UART_RxCpltCallback() when using Normal Mode. Check for UA

Hello ! I need to replace a burnt-out AL100BXP component! I can't find a retailer anywhere. Is there a compatible component or a supplier that might stock it? Looking forward to any information—thanks

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I am currently using the NUCLEO-H7S3L8 CN2 Type-C port as a USB_OTG_HS embedded PHY host/source.The TCPP03 source path opens successfully, and both the USB stick attachment and port reset are working. After the reset, HPRT reads 0x00001005, which seems to indicate speed=HS and that the port is enabled.However, during the first EP0 SETUP GET_DESCRIPTOR request: HAL_HCD_HC_SubmitRequest() = HAL_OK HAINT = 0x00000001 HCINT = 0x00000080 TXERR = 1 xfer_count = 0 The exact same issue occurs even during a raw HAL EP0 smoke test, prior to involving USBX/FileX.I would like to verify the following points: What is the mandatory clock/power initialization sequence when using the USB_OTG_HS embedded PHY host on the H7S3L8? Is it acceptable to use HSI → PLL3Q for the USBPHYC clock, or is an HSE strictly required? What are the necessary settle/wait conditions after enabling USBHSREG? Are there any required CC/UCPD configurations for the CN2 Type-C/TCPP03 source setup, apart from the PM9

I am working on a project to drive a door using a PMSM motor in position control mode. I am trying to add an emergency brake function. In an emergency, when the operator pushes a button, motor should brake and then return to its starting position without harming anyone.I know there is PWMC_TurnOnLowSides() function (https://community.st.com/t5/stm32-mcus-motor-control/how-can-i-stop-the-motor-urgently/m-p/597309#M8287 ). But it is just stopping the motor, not braking. I have tried this function.As far as I know, there is no such API in position control mode.If I am wrong, is there an API to brake the motor in an emergency? Can anyone help me? Do you have any advice for me?Any information you provide will be welcomed.   Project:ST MCW Ver             : 6.3.2STM32CubeIDE Ver : 1.18.1Driving algorithm      : FOCControl board            : Nucleo-G474REPower board        &

Hello Team,I want to store Binary files in STlink-V3 Or any other model , to flash the target on the field without host PC / Cube Programmer.I came to know , this device model has Bianary / hex file drag and drop feater , would it helpful in my scenario ?If not , Suggets any other option. 

Hello,Has anyone seen ACTCLF permanently stuck at 0 on STM32N6 despite a confirmed HS clock at the input?I have had issues with this for some time and need a little help. Pehraps the following questions could be enligtning.Are there SNPS D-PHY initialization or calibration steps for the clock lane beyond what HAL_DCMIPP_CSI_SetConfig performs? Clock-lane equivalents of the 0xe2–0xe4 DDL registers? Can ST confirm the CSI kernel clock (IC18) is the D-PHY cfg_clk, and its required range? The CCFR encoding caps at ~33 MHz and the DK example uses 20 MHz, but we couldn't find this constraint stated in RM0486. Is PTSR being permanently 0 expected on this silicon? Is there any way to verify test-interface writes landed? What exactly are the conditions for ACTCLF to assert? Does the RX require observing a complete LP-11 to LP-01 to LP-00 entry sequence after PEN, and is there a known failure mode if the LP levels at the pad are degraded (e.g., loaded by an external common-mode filter) while HS

Hello,(ST-LINK + CubeProgrammer UART/USB both failing)I am using a NUCLEO-N657X0-Q board. I cannot flashing my code via the ST-Link ( ST-Link windows driver is installed and detected through device manager and I had already updated the stlink). it throws this error:STMicroelectronics ST-LINK GDB server. Version 7.11.0Copyright (c) 2025, STMicroelectronics. All rights reserved. Starting server with the following options:Persistent Mode : DisabledLogging Level : 1Listen Port Number : 61234Status Refresh Delay : 15sVerbose Mode : DisabledSWD Debug : EnabledInitWhile : Enabled Target unknown error 32 Error in initializing ST-LINK device.Reason: Unknown. Please check power and cabling to target.Then tried with CubeProgrammer to connect via STlink but it connects then quickly drops , here is the log :17:22:24 : STM32CubeProgrammer API v2.20.0 | Windows-64Bits17:22:39 : UR connection mode is defined with the HWrst reset mode17:22:40 : UR connection mode is defined with the HWrs

in debugging mode the values of variables gets corrupted when I check in live expressions. Here corrupted means shows wrong values.

When I compile my code, I get strange errors that make no sense.#define ADC_BUFFER 1000 gives error "expected declaration specifiers or '...' before numeric constant"even though the line above it #define ADC_HIGH_THRESHOLD 3500 doesn't generate an error.HAL_TIM_Base_Start(&htim3); and HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_buffer, ADC_BUFFER); both generate "Syntax error".The TIM and ADC Start errors expanded error message is:  error: expected declaration specifiers or '...' before '&' token /* USER CODE END Header *//* Includes ------------------------------------------------------------------*/#include "main.h"/* Private includes ----------------------------------------------------------*//* USER CODE BEGIN Includes */#include <stdlib.h>#include <stdio.h>#include <stdbool.h>#include <stdint.h>#include <inttypes.h>#include "globals.h"/* USER CODE END Includes *//* Private typedef -----------------------------------------------------------*//

I’m creating a project for NUCLEO-144 (STM32H563ZIT6)and I’m using STM32CubeIDE for Build/Debug.After reading various guides from the Web, I have still notbeen able to see any Console output (trying to use printf()and re-directing the character output with this: int _write(int file, char *ptr, int len){     for (int i = 0; i < len; i++)     {          ITM_SendChar((*ptr++));     }     return len;} Is there an esoteric Config in the IDE that I need to Enable (or Disable)?Have I missed some important item in the Project Creation? (I had used STM32CubeMX)Guidance appreciated!Paul++ 

Hello,while testing 6 types of SPI NAND with MP257, I found no 1V8 part boots (tested 2, MT29F4G01ABB and AS5F18G04SND). While looking at scope traces, 32MHz clock from BootROM is almost sinusoidal.I tested booting from Engineering mode and custom BL, it boots Linux as 21MHz but not at 32MHz. IOSPEED is set to “2” (tested 3 too).Then I set bit 14 in OTP 124 (allow for <2.5V for VDDIO3) and then set PWR->CR1 VDDIO3VRSEL too. Now, it boots with 32MHz from my BL (with IOSPEED 2) and clock now seems much nicer.But BootROM seems to ignore OTP 124 and tries to use 32MHz with 1V8 and GPIO in degraded mode.Is there way to make 1V8 OSPI boot work ? Force ROM to either use slower clock or to set VDDIO3VRSEL.Thanks, Martin

Hi everyone,I'm working on a project using NASA's Core Flight System (cFS) running over RTEMS RTOS, and I need approximately 8MB or more of external RAM for the workspace/heap.Currently, I'm using a NUCLEO-H753ZI board (STM32H753ZI), which only has 1MB of internal SRAM. I've been looking for an easy way to add external RAM, but I'm running into some challenges.My questions: Is there an easy way to add 8MB+ of external RAM to the NUCLEO-H753ZI? I've looked into FMC-based SDRAM shields/expansion boards, but I haven't found any off-the-shelf solutions that work well with this board. Is there a shield, module, or expansion board I should know about? If adding RAM to this board is not practical, which STM32 board would you recommend instead? I need: 8MB+ RAM, Cortex-M7 (or similar performance), and preferably existing RTEMS/cFS support. I've seen mentions of STM32H745I-DISCO or STM32H747I-DISCO having onboard SDRAM, but I'd like community input on the best choice. My sta

Environment & hardware:STM32F722RET6:LQFP64USB3300EZKSTM32CubeIDE v2.1.1STM32CubeMX v6.17.0Windows 11 OS Description of problem:I am trying to use ULPI with external HS USB phy with the follwing schematic:when calling MX_USB_DEVICE_Init(), it will be stuck at  /* Required few clock cycles before accessing USB PHY Controller Registers */for (volatile uint32_t i = 0; i < 10; i++) { __NOP(); // No Operation instruction to create a delay} /* Core Soft Reset */ USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do { count++; if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); return HAL_OK;}in USB_CoreReset(), eventually returning HAL_TIMEOUT. Images of USBx and RCC:USBx before core soft resetUSBx after soft core resetRCC before & after soft core resetMy clock configuration, everything not included in this image is greyed outULPI pins: /**USB_OTG_HS GPIO Configuration PC0

Hello,I am currently trying to leverage STM32H753 FMC feature to interface with legacy Motorola flexbus style peripheral.I suspect the answer to my question is no but I could not find an explicit statement within documentation saying it is precluded hardware wise :Is there a mode / configuration (down to the registers level) that could allow the write enable signal (WE) to be asserted before the chip select signal (NE) ?Thanks

I’m using SPC58EC80E5 and i wanted to load the files into unit without using JTAG, so that i wanted a Bootloader, How to work on that and if any sample projects are there for reference ? I already searched for this project “SPC582Bxx_RLA Bootloader Test Application for Discovery” it was no there.In fields i should load the project without using JTAG , i have only connection with CAN.

Hello, few days ago ST MCU FINDER PC v 6.1.0 stop downloading updates with error message:It's only me, or server problem? Thank you. Regards,Slavomir Tomascik