ADC output with offset in some unknown region

[Zheng Liang]

We are migrating project from F303 to G473, but the ADC output of G473 confused us with a strange problem, and with same circuit with F303 project below:

sampling time: 66ns

sampling period: 1.16us

voltage range: 1~3V

Vdda / Vref: 3.3V

Here is thre problem curve output from ADC, the range between this two ramping point got a negative offset from original curve:

ramping points detail:

 

The output from six channels from dual ADC show that the problem presented randomly.

 

Although increasing the sampling time could cover the problem, but the sampling period is too long, we think it's not the right solution, since we used almost same sampling time on F303 project and works fine.

So what's the functional difference between F3 and G4 will cause this problem and how we solve this?

[TDK]

Is VDDA/VREF+ stable with sufficient capacitance on the line?

How far away are the sensors and does the behavior change if you alter how the wires between them run?

If you measure a constant voltage which is generated close to the chip (e.g. 1.5V), is the problem present there as well?

[waclawek.jan]

Also, read AN5346.

JW