DDR3 Ram Problems

[Niklas Voi]

Hi,

we are currently bring up our custom STM32MP157 Board.

We get in any constellation a

"DDR addr bus test: can't access memory @ 0xc000004"

We think that our crystal is correctly running at 24 Mhz because we connecting over USB to the Board. Also the Voltages is correctly. We use the same DDR Chip, that is on the DK2 ( Micron ), with the same settings.

We run a little bit out of ideas how to handle this. We also got DDR errors in Uboot SPL.

Have you any hints beyond the "Bring up" Guide?

Best regards

[PatrickF]

Hi,

did your check the HSE bypass setting in DT ?

did you have an STPMIC1 on your board ?

Is DDR_VREF present at right voltage on STM32MP1 and DDR3L ?

Are DDR_ZQ 240 ohms resistors present on STM32MP1 and DDR3L?

Are DDR_CKE and DDR_RESETN going high ?

Is there clock present on the DDR_CLKP/N ?

Regards.

[Olivier GALLIEN]

Hi @Niklas Voi​

Did you run DDR tuning Tool and apply result settings ?

Olivier

[OlivierK · Accepted solution]

Hi @Niklas Voi (Community Member)

Have you run DDR tool and applied the DDR tuning values in the DT using #define DDR_PHY_CAL_SKIP, and you have this error at boot on TF-A?

If the answer is yes, then it is a tool limitation that will be corrected in CubeMx v6.3 (limitation is present on CubeMX v6.2).

An issue has been identified regarding DQS Gating (function call missing) and will be corrected in next release of CubeMx/DDR tool (v6.3).

depending if you are in 16-bit DDR or 32-bit DDR, you need to update manually the registers below according to DQS gating values found by DDR tuning.

• DX0DQSTR,DX1DQSTR -> 16-bit DDR config
• DX0DQSTR,DX1DQSTR,DX2DQSTR,DX3DQSTR -> 32-bit DDR config

According to DQS gating values found by DDR tuning.

I hope it'll solve the issue.

Olivier

Here's the workaround.

You still can run DDR tool and apply the calibration values from the test, but you'll need to update, at most, 4 registers manually if you want to include the DQS values in the DT.

https://wiki.st.com/stm32mpu/wiki/DDRCTRL_and_DDRPHYC_device_tree_configuration

In my case (16-bit DDR)

DDR>step 3         

current step is 3:DDR_READY             

DDR>tuning 0                                  

execute 0:Read DQS gating                            

Byte 0, R0DGSL = 2, R0DGPS = 0                         

Byte 1, R0DGSL = 2, R0DGPS = 0                         

Result: Pass []

-> According to the DQS gating above and the corresponding table (shown below), I need to update manually DX0DQSTR, DX1DQSTR as follow

DX0DQSTR 0x3DB00002  

DX1DQSTR 0x3DB00002 

For a 32-bit DDR you will have also Byte2, Byte3 showing values.

update manually the 4 registers : DX0DQSTR/DX1DQSTR/DX2DQSTR/DX3DQSTR

Here's the corresponding table to update the registers according to DQS values:

Example for Byte 0 with all combinations from DQS Gating,

( same table for Byte1 = DX1DQSTR, Byte2 = DX2DQSTR, Byte3 =DX3DQSTR)  

Byte 0, R0DGSL = 0, R0DGPS = 0 => DX0DQSTR = 0x3DB00000

Byte 0, R0DGSL = 0, R0DGPS = 1 => DX0DQSTR = 0x3DB01000

Byte 0, R0DGSL = 0, R0DGPS = 2 => DX0DQSTR = 0x3DB02000

Byte 0, R0DGSL = 0, R0DGPS = 3 => DX0DQSTR = 0x3DB03000

Byte 0, R0DGSL = 1, R0DGPS = 0 => DX0DQSTR = 0x3DB00001

Byte 0, R0DGSL = 1, R0DGPS = 1 => DX0DQSTR = 0x3DB01001

Byte 0, R0DGSL = 1, R0DGPS = 2 => DX0DQSTR = 0x3DB02001

Byte 0, R0DGSL = 1, R0DGPS = 3 => DX0DQSTR = 0x3DB03001

Byte 0, R0DGSL = 2, R0DGPS = 0 => DX0DQSTR = 0x3DB00002

Byte 0, R0DGSL = 2, R0DGPS = 1 => DX0DQSTR = 0x3DB01002

Byte 0, R0DGSL = 2, R0DGPS = 2 => DX0DQSTR = 0x3DB02002

Byte 0, R0DGSL = 2, R0DGPS = 3 => DX0DQSTR = 0x3DB03002

Byte 0, R0DGSL = 3, R0DGPS = 0 => DX0DQSTR = 0x3DB00003

Byte 0, R0DGSL = 3, R0DGPS = 1 => DX0DQSTR = 0x3DB01003

Byte 0, R0DGSL = 3, R0DGPS = 2 => DX0DQSTR = 0x3DB02003

Byte 0, R0DGSL = 3, R0DGPS = 3 => DX0DQSTR = 0x3DB03003

Byte 0, R0DGSL = 4, R0DGPS = 0 => DX0DQSTR = 0x3DB00004

Byte 0, R0DGSL = 4, R0DGPS = 1 => DX0DQSTR = 0x3DB01004

Byte 0, R0DGSL = 4, R0DGPS = 2 => DX0DQSTR = 0x3DB02004

Byte 0, R0DGSL = 4, R0DGPS = 3 => DX0DQSTR = 0x3DB03004

Byte 0, R0DGSL = 5, R0DGPS = 0 => DX0DQSTR = 0x3DB00005

Byte 0, R0DGSL = 5, R0DGPS = 1 => DX0DQSTR = 0x3DB01005

Byte 0, R0DGSL = 5, R0DGPS = 2 => DX0DQSTR = 0x3DB02005

Byte 0, R0DGSL = 5, R0DGPS = 3 => DX0DQSTR = 0x3DB03005

Byte 0, R0DGSL = 6, R0DGPS = 0 => DX0DQSTR = 0x3DB00006

Byte 0, R0DGSL = 6, R0DGPS = 1 => DX0DQSTR = 0x3DB01006

Byte 0, R0DGSL = 6, R0DGPS = 2 => DX0DQSTR = 0x3DB02006

Byte 0, R0DGSL = 6, R0DGPS = 3 => DX0DQSTR = 0x3DB03006

Byte 0, R0DGSL = 7, R0DGPS = 0 => DX0DQSTR = 0x3DB00007

Byte 0, R0DGSL = 7, R0DGPS = 1 => DX0DQSTR = 0x3DB01007

Byte 0, R0DGSL = 7, R0DGPS = 2 => DX0DQSTR = 0x3DB02007

Byte 0, R0DGSL = 7, R0DGPS = 3 => DX0DQSTR = 0x3DB03007

[Niklas Voi]

Hello,

thanks for your help and advice. In the end we got a mix between different errors.

we got a hardware issue on layout. We are now at a point, that the kernel starts and getting the system up.

best regards,

Niklas