SPI Discrepancies

[NSR]

Hi

I'm trying to read an EEPROM connected to SPI1 and facing difficulties. For some reason the clock is off by being idle high. This doesn't happen if I use SPI3 and am therefore wondering if there's some characteristic or further configuration that is required with SPI1?

Note that I'm using PA4 for both scenarios but this is a manual process anyway; send PA4 low, interact with SPI, send PA4 high. However, I cannot see this being an issue. I've attached a couple of images showing the results as follows:

SPI1 (bad):

 

SPI3 (good):

 

I've gone through a number of settings within the configuration and my setup is as follows:

SPI1

Mode: Full-Duplex Master
 
Hardware NSS Signal: Disable
 
NVIC SPI1 global interrupt: Yes
 
DMA: None
 
GPIO:
PA5: SPI1_SCK
PA6: SPI1_MISO
PA7: SPI1_MOSI
 
NVIC SPI1 global interrupt: Yes
 
No DMA
 
GPIO
 
Frame Format: Motorola
Data Size: 8 Bits
First Bit: MSB First
Prescaler: 32
Baud Rate: 15.0 MBits/s
Clock Polarity (CPOL): Low
Clock Phase (CPHA): 1 Edge
CRC Calculation: Disabled
NSSP Model: Disabled
NSS Signal Type: Software
Fifo Threshold: Fifo Threshold 01 Data
Tx Crc Initialization Pattern: All Zero Pattern
Rx Crc Initialization Pattern: All Zero Pattern
Nss Polarity: Nss Polarity Low
Master Ss Idleness: 00 Cycle
Master Inter Data Idleness: 00 Cycle
Master Receiver Auto Susp: Disable
Master Keep Io State: Master Keep Io State Disable
IO Swap: Disabled: Disabled
 
Using PA4: SPI_nCS

and SPI3:

Mode: Full-Duplex Master
 
Hardware NSS Signal: Disable
 
NVIC SPI3 global interrupt: Yes
 
DMA: None
 
GPIO:
PC10: SPI3_SCK
PC11: SPI3_MISO
PC12: SPI3_MOSI
 
Parameter Settings:
Frame Format: Motorola
Data Size: 8 Bits
First Bit: MSB First
Prescaler: 32
Baud Rate: 15.0 MBits/s
Clock Polarity (CPOL): Low
Clock Phase (CPHA): 1 Edge
CRC Calculation: Disabled
NSSP Model: Disabled
NSS Signal Type: Software
Fifo Threshold: Fifo Threshold 01 Data
Tx Crc Initialization Pattern: All Zero Pattern
Rx Crc Initialization Pattern: All Zero Pattern
Nss Polarity: Nss Polarity Low
Master Ss Idleness: 00 Cycle
Master Inter Data Idleness: 00 Cycle
Master Receiver Auto Susp: Disable
Master Keep Io State: Master Keep Io State Disable
IO Swap: Disabled: Disabled
 
Using PA4: SPI_nCS

Can appreciate that immediate thoughts would be to stick with SPI3 but unfortunately there is functionality required using the GPIO port C pins and therefore really needs to go onto SPI1. Any thoughts, insight and suggestions would be greatly appreciated.

[TDK]

Ensure the SPI peripheral is enabled (SPI_CR1_SPE) before setting CS low. It needs to be enabled to output a clock signal.

[NSR]

Thanks for taking the time to respond.

I do seem to be getting a clock ok, just that it seems to be idle high. Everything is configured using CubeMX and the CubeIDE to configure the peripheral and generate the code. Other than changing the GPIO pins, everything is the same between SPI1 and SPI3, except it works no problem with SPI3. It seems that SPI1-3 can also​ function as I2S and therefore I was wondering is there was any other possible functionality that could be interfering and causing this anomaly?

[waclawek.jan]

What hardware?

Don't use Cube. Write your own SPI routines, start with polling.

JW

[NSR]

Oops, thanks for pointing out that missing info.

I'm trying to get this working on the STM32H743ZI2 Nucleo board.

[TDK]

Did you check the SPI_CR1_SPE bit at the time you toggle CS?

> I do seem to be getting a clock ok, just that it seems to be idle high.

I wouldn't call that ok.

[NSR · Accepted solution]

Hi

Thanks again for responding and sorry I've not updated sooner. Yes, I checked but more importantly I found that the connection was a little dirty; a quick clean and everything appears to be working fine now.