Pipeline stage explanation

[AMat.1]

hi, all. I wanted to ask about The pipeline stages in the m cortex processors , i read that m0 has 3 stages and m0+ has 2 , which renders it more efficient , can anyone explain what that means?

[Tesla DeLorean]

It basically means that the execution of an instruction is broken into smaller bite size pieces. An instruction might claim to execute in "one cycle", but that basically means one can enter the pipe at a time (throughput) and might take 3 - 7, or whatever, to actually complete, but can be clocked at much higher rates because the work done in each piece of the pipe is more limited/constrained.

I'm sure the mechanics here would be explained in even the most basic college level text about MCU/CPU Architecture/Design..