Posted on September 12, 2016 at 07:09Hi Everyone,
I am currently trying to implement a SSI slave using a STM32F0(72RB) microcontroller. For those who are not familar with SSI: SSI is used as a sensor (encoder) interface for high speed applications (up to 2MBit/s). SSI works mainly as a shift register. The master produces a clock signal whereas the slave sends a bit every clock. (See details at
https://en.wikipedia.org/wiki/Synchronous_Serial_Interface ). It looks perfectly like a SPI slave in TX-Only mode without ChipSelect/NSS signal. But there is a big problem. When using DMA, it could be realized with minimal processing time.
To reduce effects like jitter when using the SSI value for a closed loop regulator, the value within the shift register should be as new as possible. Sadly, the F0 has a SPI FIFO buffer which prevents one to replace the actual value in the SPI TX register. According to the docs and several entries in the WWW I need to disable the SPI, assert a reset signal to the peripheral and fully reinitialize the SPI.
As I can detect a transfer (which is initiated by the master) at the first falling edge of the clock signal, I have about 500ns before the first valid bit needs to be available on the data line (MISO).
My question: Is there any other possibility to clear the SPI TX FIFO without a full reset+reinitialization?
Best regards,
Carsten Schumann
#stm32-ssi-spi
