Product forums

Hi, there,we recently development a set up using vl53L1CB to measure water level.During our test the sigal noise ratio is pretty good(1000/1), however, we got a very close distance (20-30mm) at real distance around 6-8m. Similar phenomenon did not occur at solid surface even at 8m.And also, since we got a pretty good measurement at 8m with a solid surface, is there any possibility that we can break the firmware limit to reach a even longer distance?Is there any possible suggestion?thank you

Hello everyone,I'm trying to establish communication between an IO-Link master and an IO-Link device, but I'm very new to this field and I'm having a lot of difficulty getting the communication done.I'm using a STEVAL-IOM001V1 with the L6360 transceiver. I generate an 80 µs wake-up pulse on the bus using a timer in alternate function with the USART. Then, through my state machine, I'm able to send a Type_0 message with MC = 0xA2 and the corresponding checksum at different transmission rates, while keeping the Tdmt timing between consecutive messages within the required range of 27–37 Tbit.Using an oscilloscope, I can see that the wake-up sequence (Twup + Tren) and the messages are correctly generated and transmitted to the device. However, in most cases, the device does not respond.As the IO-Link device, I'm using an X-NUCLEO-IOD02A1 with the L6364Q transceiver and the ST example software with the MiniStack.Has anyone experienced a similar issue or have any suggestions on what I might

The chip is STM32G473VET6. When enabling opamp1 in independent mode, I found that the VINM pin can switch between PA3 and PC5. But if you enable independent mode and also connect Vout to the internal ADC channel, you'll find that VINM can only be used on PA3. How should I understand this phenomenon?From AN5306 Figure 18, you can see that you can switch using VM_SEL[1:0] and OPAINOTEN[0]. Does this mode have any limitations? 

I have created a new project based on the STM32G491 and have used ADC1 to create eight ADC inputs.The only option I have presented for ADC Scan Mode is Disabled. What do I need to do to enable Scan Mode please?Kind regards,Al 

Hi everyone,I am trying to generate a professional SBOM for my project.I have a few questions regarding the best workflow:Tooling & Detection: What the best tool to generate the SBOM.I tried using ScanCode, but it didn't find any component in my project (e.g., FreeRTOS). I had to manually add .about files to the folder to get results. Is there a better tool that can generate the SBOM with minimal manual intervention?ST Cube SBOM : The Cube MCU packages contain dozens of libraries (FatFS, FreeRTOS, USB_Host, etc.). If my project only uses FatFS, the package JSON still lists everything. Do I have to manually extract the components I use from the ST JSON? how to get use of the ST SBOM?I’d love to hear if anyone has a script or a specific toolchain that automates this without the manual "copy-paste" from the ST manifests Thank you!Yahya  

I simply can't figure out how to generate this pulse with my STEVAL-IOM001V1 board. Even the supplied code (en.stsw-iom001) doesn't make me any wiser.

Hello,I am using an STM32L431 as an I2C Slave and an RL78/G13 as an I2C Master.I am trying to transmit data from the STM32L431 (Slave) to the Renesas RL78 (Master).When the RL78 performs an I2C read operation, the following callback sequence is observed on the STM32: 1 HAL_I2C_AddrCallback(Direction = Read) 2 HAL_I2C_ErrorCallback(ErrorCode = 4) 3 HAL_I2C_ListenCpltCallback()Inside the AddrCallback I start the transmission using: HAL_I2C_Slave_Seq_Transmit_IT(hi2c, tx_buffer, tx_length, I2C_FIRST_AND_LAST_FRAME);The function returns HAL_OK.The transmit buffer contains a simple incrementing pattern, length 20 byte: 01 02 03 04 05The STM32 reports that transmission has completed: XferSize = 20 XferCount = 0However, immediately afterwards the ErrorCallback is called with: TextErrorCode = 4According to stm32l4xx_hal_i2c.h this corresponds to: HAL_I2C_ERROR_AF (Acknowledge failure / NACK).On the RL78 side, the receive buffer does not contain the transmitted data. Expected: 01 02 03 04 05 ..

I am using 4 HRTIM PWM outputs(CHA1/A2 and CHB1/B2) on the STM32G474 MCU to control a full-bridge converter. I want a delayed version of the PWM on CH1A using another advanced/basic timer. Can the HRTIM generate a software interrupt which can be used by another advanced/basic timer for a delayed/phase shifted PWM output? I do NOT want to use another timer from the HRTIM module as they are reserved for other purposes.  

Hi there !I have a quick question about where the data are save. If i create one const array [1024] the data inside the array (because i write the word const in front) are save inside the falsh ? and this give to me more space in the ram  right ? and is the same if i create one struct and i acces with pointer ?  and please some one can help me and show where i can find all this kind of information like book tutorial website youtube ectThank you Sergio

My problem: my SPI2 module doesn’t appear to be clocking in data even if it is configured a full duplex master.Context:I am developing the firmware on a board that some other team designed and they picked PB13 (SCK), PB14 (MISO) and PB15 (MOSI) to implement SPI2.  I am aware of the fact that those pins are shared with the UCPD dead battery detection feature and that:Dead battery detection must be disabled Clock rate of SPI is limited to ~3MBdI am developing my drivers bare-metal (no LL or HAL), but since I couldn’t figure out how to make this work, I decided to try with the HAL code generated by STM32CubeMX.I created a new project on that software with software package v1.7.0 which appears to be the latest at this time.I simply configured the clock tree to use HSI (64MHz) → /2 → PLL1 (M=4, N=24, Q=4) = 48MHz.  I then use SPI2 prescaler to get 1.5Mbd out of PLL1Q (I tried lower data rate too).  The SPI module is configured in full duplex.  Here is the main function code after HAL initia

Dear Community, I’m struggling to find a way to prevent SMDCube IDE code generation to overwrite a changed #define. I’ve tried the usual wrapping with /* USER CODE BEGIN …   with no result, and also try to dig online for some similar issue, but no luck.Any hint on how I can actually make this work? Details:STM32U595STM32CubeIDE Version: 1.19.0 specific define ( in STM32U5xx_HAL_CONF )#define USE_HAL_ADC_REGISTER_CALLBACKS 1U /* ADC register callback disabled */this one is overwritten each time code generation is run from the graphic GUI Goal is to have ADC complete callback registrable to multiple functions. When I force the above define to 1, all works as expected, but when I have to run code generation then the define is rolled back to the standard “0U”, which obviously is not desirable.Tried also to override the define from outside the file, but this creates a neverending chain of errors. Best Regards,Anton 

Dear ST Team,We would like to request the design files and technical documentation for the STEVAL-ISD01KCB – 22 kW High-End Servo Drive SIL2 Reference Design for evaluation and reference purposes.Kindly share the available design package, including schematics, PCB layout files, BOM, Gerber files, firmware/software package, hardware architecture documentation, technical specification, safety assessment documents, STO (Safe Torque Off) and SBC (Safe Brake Control) implementation details, TÜV safety documentation, and any other related technical documents.If access to these materials requires an NDA, please let us know the process for obtaining access.We appreciate your support and look forward to your response.Best Regards,Maryam

First i'll say what i have. I have folders name 34,35,37,38,39,42. Inside it has images adn every folder images start with 0. I have a folder name DWIN_SET. So inside that DWIN_SET it has 22_Config.bin,14ShowFile.bin, 13TouchFile.bin,32 icon library these are generated by me few mins back. Remaining files are old files which is already present. What i did is Open the DGUS software. and open .hmi which is present outside the DWIN_SET. after opening it shows a list of 6 images, among that first image is different, it is inbuilt someone kept that order, i didn;t change anything on this. I opened a folder named image, inside it has 32,34,35,37,38,39,42 folders and has some images on it . What i did open the 32 folder in ICL generator tool. Here i try to remove only one image which 0.png and replace it with another image present in different folder, but it failed. If i change one image remaining all iages also lost. So what i did is replace the image in the folder and then open it in icl to

 I am working with an STM32F0 device and I want to implement a firmware update mechanism.My current plan is to split the internal flash into three regions:Bootloader: 0x08000000Application Slot 1 (App1): 0x08004000Application Slot 2 (App2): 0x08008000The bootloader always runs first.Only one application slot is active at a time.The update flow is planned as follows:If App1 is currently running and a new firmware update arrives, the new firmware is written to App2.If App2 is running, the new firmware is written to App1.After the update, the bootloader selects which slot to boot.My concern is about the linker script (.ld) configuration:When I build a new application firmware, I set the flash origin address in the linker script to:  FLASH (rx) : ORIGIN = 0x08004000This works correctly when the firmware is programmed into App1.However, if the same binary is written to App2 at address 0x08008000, the vector table, reset handler, and absolute addresses inside the firmware will

Hello,I downloaded STM32CubeN6-main FW 1.4.0 from GitHub and am trying to build the Nx_WebServer FSBL example.  I am getting this error message:11:26:53 **** Build of configuration Debug for project Nx_WebServer_FSBL ****make -j16 all make: *** No rule to make target 'C:/STM_FW/STM32CubeN6-main/Middlewares/ST/threadx/common/src/tx_block_pool_performance_info_get.c', needed by 'Middlewares/threadx/Performance/tx_block_pool_performance_info_get.o'. Stop."make -j16 all" terminated with exit code 2. Build might be incomplete.11:26:55 Build Failed. 1 errors, 0 warnings. (took 2s.214ms)I don’t see any source code at the C:\STM_FW\STM32CubeN6-main\Middlewares\ST\threadx location, is there another project I need to build first?

Hello!I attempted running a basic FreeRTOS example on a STM32F407VET6 board using CMSIS v2 following some tutorials, replacing systick for either TIM 6 or 7 as HAL Timebase as many tutorials suggest. The code only blinks and LED on the pre-generated task.I could never get the program to work and by pausing execution I noticed it went straight to the default handler infinite loop. After reading a few posts it seems that the CubeIDE still does not generate the appropriate timer IRQ Handler within the stm32xxxx_it.c file and has to be added manually, as suggested by @Curtis B. on the posts attached bellow. void TIM7_IRQHandler(void) { /* USER CODE BEGIN TIM7_IRQn 0 */ /* USER CODE END TIM7_IRQn 0 */ HAL_TIM_IRQHandler(&htim7); /* USER CODE BEGIN TIM7_IRQn 1 */ /* USER CODE END TIM7_IRQn 1 */ } Adding the IRQHandler fixes the issue but it is a bit frustrating that many tutorials follow the same steps and rarely mention this, since it usually works fine with other MCU

I’ve been trying to adapt the code from the STM32WB5MM-DK QSPI_ReadWrite_IT example to a Renesas part. However, I have not been able to get it into Quad mode. For this part I need to write 0x02 into register 0x31 as I understand the data sheet.From monitoring the status register I can see that the write enable bit gets set and cleared, but the QE (quad enable) bit doesn’t get set.Also, in reviewing the code for the DK, I don’t see code to set the quad enable bit as per the Infineon S25FL128S data sheet.In searching the support forums, I see references to a routine called QSPI_QuadEnable, but I have not been able to find corresponding code.I’m obviously missing something. Can someone point me in the right direction - either specific to this board or a more generic solution?Thanks

Hello, everyone on the forum.I'm building a system using the STM32H735G-DK, ThreadX, and NetX Duo.I'm writing logs to a microSD card to keep a record of the system's operation.I integrated FTP into the system so that log files can be downloaded via Ethernet.Since the FTP download speed is only about 150 kilobytes per second, it takes a long time to download large log files.Currently, `nx_ftp_server_create` allocates an 8K-byte stack for the FTP server. What are some ways to increase FTP download speeds?I would appreciate any advice. 

Hi,don't  know if it reaches someone who is responsible, but just some thoughts about the datasheets of all the VL53… which i have seen:the NXP documents about I2C which are the defacto standard are stating an address is 7 or 10 bit. So it’s not a question how some microcontroller is handling bit shifting or internal storage of the address, the address of the vl53 is 0x29, not 0x52. If you use Philips/NXP protocol you should follow it’s specification. Please use this in your datasheets.if you talk about SPI it is common to use POCI/PICO or MOSI/MISO and CS/SS/CE…. Why you don’t use the common names for slave select? What should NCS be? Noncommunication Chip Select? Why you transcribe MOSI as "main out secondary in" instead of using common "master out slave in"? If you want to distance yourselves from these terms because of their connection to slavery, then why not use POCI/PICO with "peripheral out/controller in” and vice versa as common.why you describe pins as GPIO if they no one can

Hello, I intend to use two 8-bit DDR3L memory devices with the STM32MP257FAK3. Could you kindly confirm whether this configuration is supported? Looking forward for your response. Regards,Shubham 

I am trying to establish an accuracy figure for our product based on an MPX5500 MEMs pressure sensor.We calibrate at many set pressures across the devices span, so we can reduce non linearity errors.I need to determine the sesnors accuracy with improved non-linearity figues but need to know error corficients for aspects such as temperature, hysteresis, aging etc     There is talk of an orignal “sensor development kit” ASB200 from Motorola (Freescale, then NXP), which had SPICE model.Does anyone know of this kit or have the SPICE models available?Or any other application notes that might help?Thanks. 

I was learning about how the PLLs work on the H7RS boards, and I discovered a small inconsistency in the RCC_PLLCFGR register. On page 440 and 442 of the RM0477, PLL2FRACEN is incorrectly written down as PLL2FRACLEN (including the ‘L’ near the end). I’ve confirmed that this is incorrect by looking at the HAL and seeing it’s consistently defined as PLL2FRACEN in code (without the ‘L’) inside of stm32h7s3xx.h. Searching for the version with the ‘L’ returned no results, so I’ve concluded that this must be a typo in the reference manual. Could you confirm this is a documentation typo?

Hi,I am using an SPC560B40L5 with ChibiOS/AutoDevKit Studio.The hardware design is already finalized, so I cannot change the wake-up circuitry. Because of this limitation, I use the RTC to wake the MCU periodically every 200 ms. After each wake-up, I only check a few GPIOs to determine whether a real wake-up event has occurred. If no event is detected, the MCU immediately enters STOP mode again. No peripherals are reinitialized unless a valid wake-up event is detected.The sleep/wake-up sequence works correctly during normal operation. However, I am facing a strange issue after reprogramming the MCU.After downloading new firmware (without removing power), the MCU freezes in:while (ME.IS.R == 0U){}inside:SPCSetRunMode(SPC5_RUNMODE_STOP);The board must support in-field reprogramming through the diagnostic interface (without a power cycle), but after programming the MCU usually remains stuck until the power is removed and applied again.Interestingly, if I disable the periodic RTC wake-up a

I am trying to establish communication between an STM32F446ZCH6 and a LAN9253 using the Quad SPI (QSPI) interface on our custom hardware.As an initial validation, I am attempting to read the following LAN9253 registers: BYTE_TEST register (0x64) ID_REV (Chip ID) register (0x50) However, I am not receive the expected register values. Instead, the values returned are consistently 0x88888888 or 0xFFFFFFFF.To troubleshoot the issue, I captured the SPI/QSPI communication using a logic analyzer. From the waveforms, it appears that: The STM32 (master) is transmitting the read command correctly. The clock (SCK) and chip select (CS) signals appear normal. However, the LAN9253 does not respond with valid data, and the STM32 does not receive any meaningful data from the slave. We also attempted communication using: Single SPI (1-bit mode) Dual SPI (2-bit mode) Quad SPI (4-bit mode) Unfortunately, the behavior is the same in all three modes, with no valid response from the LAN9253.We hav

Hello Sir/Ma’am,I am planning to interface two 8-bit DDR3L memory devices with the STM32MP257FAK3. Kindly confirm whether this configuration is supported by the STM32MP257FAK3.If supported, I would appreciate your guidance on the recommended implementation approach for this configuration.Thank you for your assistance.Regards,Shubham Kawadkar