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Dear ST Support Team,I am developing a custom bootloader for the STM32L071CBY6TR (128 Kbyte, dual-bank Flash) and I have a question regarding the exact behavior of the Flash controller that I could not fully clarify from RM0367.Context:- My bootloader occupies the first 32 Kbytes (0x08000000 - 0x08007FFF), entirely within Bank 1.- My application occupies 96 Kbytes starting at 0x08008000, which means it spans across the Bank1/Bank2 boundary at 0x08010000: the last 32 Kbytes of Bank 1, and roughly 64 Kbytes of Bank 2.RM0367 states that read operations from one bank can be performed while write or erase operations are performed on the other bank (cross-bank read-while-write). However, I could not find documentation describing the behavior when a write/erase operation is performed on one bank while code execution (instruction fetch) continues from a *different page within the same bank* — which is exactly my bootloader's situation when it needs to erase/program the tail portion of Bank 1 t

Hello wonderful ST Community!Before I get into the question, a bit of background on this project. I'm creating a button panel HID gaming device for the space sim Elite Dangerous. Using its somewhat limited API I'm hoping to feed info about the game state back to a 9 inch screen on the HID device through USB CDC running composite with HID. Before I start getting into hardware dev I want to create a sim of the GUI to test two things:- size of display needed to show what I want to show- getting data out of the game (will be done with a USB CDC app/driver/python (I have not quite got this far) running on the host computer)It would be amazing to test these two aspects using the GFX simulator. I known it's theoretically possible to send data through some medium such as sockets but how does this work in practice?Is there some good documentation around how the simulator works and how I can feed data into my sims?I've been investigating using VSCode since GFX already has compatibility, but how

I need to transfer files from my hardware (STM32H723 based) and a PC, using an USB port, just like an USB disk; my hardware uses a FT234XD USB interface chip (UART connection) and an EEPROM where I save the data.Anyone may help me to understand how to do it ? Thank you

Hiya. I’ve been trying to implement a double buffer with the GPDMA for a week now. I’m trying to capture an image using DCMI. I can get it to work with a single buffer, but I have not been able to get it to work with two LL nodes and two buffers.I want the GPDMA to go between bufferA and bufferB, so I can process the alternate node i.e., if the DMA is loading into buffer B, then I process A. A simple ping-pong.I’m not sure how I’m supposed to alter my current approach with a single buffer to two. This is what I have for my linked list setup in MX_DCMIQueue_Config.... pNodeConfig.SrcAddress = 0; pNodeConfig.DstAddress = (uint32_t)bufferA; pNodeConfig.DataSize = DB_SIZE_WORDS; /* Build DCMI_Node1 Node */ ret |= HAL_DMAEx_List_BuildNode(&pNodeConfig, &DCMI_Node1); /* Insert DCMI_Node1 to Queue */ ret |= HAL_DMAEx_List_InsertNode_Tail(&DCMIQueue, &DCMI_Node1); /* Set node configuration ################################################*/ pNodeConfig.DstAddress = (uin

What is the MSL Level for part STM32G030F6P6 in a TSSOP package?

Hi everyone,I’m working on an STM32 project using STM32CubeMX and STM32CubeIDE. Everything builds and runs correctly right after generating the project, but after closing and reopening the project I sometimes run into build errors related to generated files or missing libraries.Regenerating the code usually fixes it, but I’m trying to understand why this happens in the first place.Has anyone experienced something similar with CubeMX projects? Is there a recommended way to organize the project or CubeMX settings so that generated files and middleware remain consistent when reopening the project?I’d appreciate any advice or best practices from people who work with STM32CubeMX regularly.

I would like to clarify the data constraints for Benchmark workflow in NanoEdge AI Studio:What is the maximum supported number of lines for each imported CSV dataset during Benchmark?Is there any official documented hard limit on the number of rows, or only practical recommendations?Some community references mention a rough threshold of ~100,000 lines, and files exceeding this size may cause memory overflow, import truncation or failed Benchmark launch. Could you confirm whether this threshold is formally defined?

Hello, I am using the stm32g47ret6 microcontroller and I am having troubles with transmitting and receiving data using the USART2 to my PC through the ST-LINK V3-SET. If I understand correctly, I left the v3-set configured as default (did not change the jumper configurations). I used MX to configure the usart2 module and used vcp_rx and vcp_tx for communication, used the pins PA3 and PA2 and also configured them in MX. I checked the baud rates, COM Port in my device manager. I am using tera term 5 to read the data, but I get a blank screen every time I start the program. To debug this, I tried probing the pins using an oscilloscope and I do see some repeated pulses, the baud rate matches and Uppercase 'U’ does give a square wave. I also checked the UART transmit status which shows HAL_OK in live expressions in the CUBEIDE. I am using a custom hardware board with the stm32g474ret6 mcu, it is connected to the st-link via the stdc14 connecter. This is the schematic for it.  Below is the c

 Hi, looking to power the NUCLEO-F767ZI off another board (which has a TPSM843320 buck), any issues with this as the 5V rail (E5V), on the dev board you have LD1117 LDO, but the rail I can provide isn’t high enough for the dropout.  Any spec on ripple or how clean the E5V rail should be? Seems to only be used by STLINK and USB.

I see the USBX/FileX/LevelX middlewares are supported in STM32CubeMX2, but ThreadX (formerly AzureRTOS, formerly ThreadX) itself is not? Is ThreadX support on the roadmap for the STM32C5 series? I really don’t want to have to go back to using FreeRTOS.

Hello,I am using the VDx1943 EVK kit and would like to extract the live camera feed using the SDK. Could you please help me identify the correct DLL file to use?So far, I have tried using:st_brightsense_sdk_vdx193.dll en.STSW-IMG507_16GZUnfortunately, I have not been able to successfully pull the live view with either of these. Could you point me to the correct DLL file, or advise on the proper method to extract the live feed from this kit?Thank you for your help.Regards, 

The HTS221 is marked as Obsolete, and the only suggested alternative is SHT40-AD1B - a 3rd-party device. Has ST abandoned this product area?

Hello everyone,I'm working on an application using a motor with a nominal speed of 1850 rpm and a nominal current of 4.1 A. The motor operates within a speed range of 300 to 800 rpm, and I'm looking to implement stable and efficient speed regulation.I have already imported my project into MC Workbench and configured the following parameters: Current configuration:Speed sensing mode:Speed Sensor Mode: Hall SensorSpeed regulator:Execution Rate: 1 msTarget Speed: 648 rpmAuto Calculate Kp & Ki: enabledKp ≈ 14.96Ki ≈ 0.0105Maximum speed error before fault: 3Current regulators (Torque/Flux):Execution Time: 50 µsControl Mode: Speed controlCut-off frequency: 6000 rad/sAuto Calculate Torque/Flux Kp & Ki: enabledIq (Torque) Regulator:Target: from speed regulatorKp ≈ 7.62Ki ≈ 0.326Id (Flux) Regulator:Target: 0 AKp ≈ 7.62Ki ≈ 0.326Modulation:Selected modulation: NonePWM and current sensing:PWM frequency: 20 kHzCurrent sensing gain: 21Measurement rang

I am trying to increase the cpu speed of a custom board with stm32h743VIT6 and 16mhz crystal. However, once I change the speed, the UART output prints out gibberish. I have verified the UART works with the HSI at default speed of 64Mhz. Attached is the code and board schematics. Thanks for the help. 

After I updated to CubeMX Version 6.18.0 (and newer CPU firmware pack 1.13 but this one not related to issue) I opened my older project and migrated to newer version. As a result I got error on Clock Configuration Page (see pic.1).pic.1I saved project and checked if anything changed... I did not hound any changed, but versions (see pics. 2 and 3) pic.2pic.3So, I downloaded older version 6.17.0 and there is no such issue. See pic.4 and pic.5 shows RCC block config. pic.4pic.5 RCC block config 

Error downloading crdb.zipI have tried on both STM32CubeMX 6.18.0 and STM32CubeIde 18.1. Attempting on MacOS(Intel)Tried changing proxy server type to “Use System Proxy Server” Tried different networks. Tried removing cache directories. Tried deleting crdb.zip Previous posts mention downloading (http://xsel.stmcufinder.com/refresh/v2/crdb.zip) manually - appears to be a server issue?Any help appreciated… thanks 

Dear STM Engineer, thank You very much for Your great effort  for the new STM32V8. My comments on the features after looking into stm32v8-presentation.pdf: - STM32V8 will have a ETH-Gb-MAC with PTP, that is great news for applications in the field of scientific instrumentation. -- I am missing PTP-Timestamp-capture-peripherals to generate PTP-precise timestamp input-pulse captures on external events. So triggered by one GPIO input-pulse-edges  (or better several logic-combined GPIOs, at least two to have one "gating), a timestamp (64 Bit or more?) should be stored, including in its timestamp-word at least two (better four or more) GPIO Input-states: state high/low AND edge falling/rising. We would need as many as possible of these PTP-Timestamp-capture-peripherals as possible, e.x. 16 or more of them per MC. Would You consider to include such PTP-Timestamp-capture-peripherals into STM32V8? - -  I am missing PTP-output-pulse-peripherals to generate PTP

 In STM32H7 MCU FW, i am implementing the GPDMA transfer to XSPI in indirect mode, updating DR Register from FW with DMA. I have a custom x8 SPI DDR Slave as target. The issue is i am getting Data transfer error during the HAL_DMA_Transmit_IT function. I have refered the app note for GPDMA - AN5593 where it is mentioned as -  on page 38. I am using SW based trigger to dma since there is no GPDMA req signal for xspi for STM32H7. I want to knowhow to implement software-based trigger if gpdma req signal is not present. I have mentioned the code below. IF there is any workaround to fix the HW DMA req signal issue from xspi? If not then on what other STM device having min of 2 - x8 spi support proper GPDMA transfer with HW DMA req implementation. Code used in my application is mentioned below - static void MX_GPDMA1_XSPI2_TX_Init(void){    __HAL_RCC_GPDMA1_CLK_ENABLE();     hdma_xspi2_tx.Instance = GPDMA1_Channel0;   // use typed instance macro     hdma_xspi2_tx.Init.Request               =

Hello,We are designing a custom board using the STM32MP157FAC1 and have used the STPMIC1APQR PMIC to power the microprocessor, similar to the STM32MP157F-DK2 evaluation board.We need to provide a Power LED on the front panel of the card to indicate that all the power rails generated by the STPMIC1APQR are operating correctly.Since the STPMIC1APQR does not provide a dedicated Power_Good (PGOOD) output signal, we are considering using the RSTn pin (Pin 1) to drive the Power LED along with its connection with NRST pin of STM32MP157FAC1. Our understanding is that RSTn is released (driven high) only after the power-up sequence has completed successfully and all required power rails are within specification. If any monitored power rail fails, RSTn would be asserted low.We plan to use a transistor stage to drive the LED from the **RSTn** signal so that:(1.) RSTn = High: Power LED ON(2.) RSTn = Low: Power LED OFFCould you please confirm whether this is approach is okay or not ? If not, kindly

Figure 14 - Operating modes transition diagram - does not show it: and neither does Table 16 - Operating modes transition criteria: The description of the “reset mechanism” doesn’t really relate to the above state diagram or table: 

Hello ST Community, I noticed that when using the benchmarking tool, datasets larger than 250 MB are automatically reduced using a "representative sampling strategy" that preserves the diversity and distribution of the original data. I would like to understand more details about this process: 1. What specific sampling algorithm/strategy is used? (e.g., random sampling,    stratified sampling, systematic sampling, etc.) 2. How is the target size of 250 MB determined? Is this configurable? 3. How does the tool ensure that the sampled dataset preserves:   - The original data distribution?   - The diversity of data samples?   - Edge cases and boundary values? 4. After optimization, when we validate the model on the full dataset, what    performance differences should we typically expect between the sampled    dataset and the full dataset? 5. Is there any documentation that describes this sampling mechanism in detail? Any information or pointers to relevant documentation would be greatly ap

how can we go initial stm32N6?

Using on a STM32H563RI with trustzone for a secure bootloader and non-secure application. Both the secure and non-secure side were correctly working in OPEN state, and I did a test of going to a CLOSED state and regression back to OPEN with authenticated debug. After the regression, RTC_EnterInitMode(), times out trying to enter init mode and HAL_RTC_Init() fails. I tried the solution from this form post of calling HAL_PWR_EnableBkUpAccess() and that did not work.Notes:- Trustzone and the secure watermarks for the bootloader were reprogrammed in the option bytes after regression.- RTC is LSI as its clock source.- The call to HAL_RCCEx_PeriphCLKConfig() in HAL_RTC_MspInit() returns HAL_OK.- The RTC pheripheral is marked non-secure.- The code has not been changed since preforming the regression and was working previously. The RTC Init Code and Clock configs are included below.void MX_RTC_Init(void) { /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */

Setup:I have a CubeMX/CubeIDE-generated STM32G474RET6 project (ThreadX) that I build as a static archive rather than a flashable executable, meant to be linked into a separate top-level consumer application. The consumer supplies main(), calls into this library's init function, and never defines its own vector table, interrupt handlers, or MSP callbacks — this library owns all of that. Problem:A static archive only pulls in the .o members something already-linked actually references (need-driven extraction). That interacts badly with two CubeMX-generated weak-symbol patterns: Vector table vs. stm32g4xx_it.c: startup_stm32g474retx.s gives every handler a .weak/.thumb_set XXX,Default_Handler fallback, satisfied locally from the always-linked startup object. Since nothing else references handlers like NMI_Handler or a peripheral's IRQHandler, the linker never has a reason to pull stm32g4xx_it.c.o out of the archive — the real handlers in it are silently dropped in favor of Default_Handler

I am using an LPS22DF over I2C with an STM32WB5MMG. The sensor is configured for continuous 1 Hz operation, AVG = 64, LPF1 = ODR/4, and continuous dynamic-stream FIFO mode. FIFO samples are retrieved as separate three-byte reads from registers 0x78–0x7A.The first FIFO read after every watermark interrupt is consistently corrupted by approximately +32 hPa. For example, the first value may be raw 4130956 (1008.534 hPa), while the following values are approximately raw 3999700 (976.49 hPa) and agree closely with the standard PRESS_OUT registers. The difference is close to 131072 counts, corresponding to bit 17 of the 24-bit pressure value. This occurs repeatedly for every FIFO batch, not only during startup or LPF settling.  Our operational workaround is to set the FIFO watermark to 11, read eleven three-byte data sets individually, discard the first result, and average the remaining ten. Is this first-read corruption a known LPS22DF behavior or erratum? Is there a required FIFO read sequ