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RefMan RM0522 version 1.0 seems to conflict with the datasheet DS15137 - Rev 3 and DS15136 - Rev 1.RM0522 Table 23 says that all three calibration values (Vrefint, TS_CAL1 and TS_CAL2) are stored as 32-bit words.Both Datasheets’ sections 5.3.5 specify the Vrefint calibration value as 24-bit. (?! - looks like a mistake)Both Datasheets’ sections 5.3.20 show the TS_CALx values as 16-bit, as in most of other STM32 models.

We used to define STM32 pinout in STM32CubeMx since it's aware of all the possiblilities of the MCU.Then we manually need to transfer the pnout into Altium Designer Schematic. And to keep those in sync when design changes.So we want to automate that step if possible.Thus the question: How can I Import pinout generated from STM32CubeMx into Altium Designer Schematic.

Page 47 Figure 15. GND Plane: GND plan instead of GND planeGuidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs - Application note Can’t attach a screenshot for some reason

I have many timers working on out H743VIT6 board, so only have Tim2, 5, 12 and above available.I have many forms of of timer triggered DMA working, but in this case as the system is near to max capacity, I need a DMA event scheduled for 52uS in the future WITHOUT using IRQs which are not time-stable enough for the purpose.So I found that timer 16 in table 98 of the RM0433 manual is show connecting to timer 2, but in CubeMX timer 15 shows no trigger source!So I though I would set up timer 5 to count down 52uS and trigger its DMA stream to write a half word to CR1 of Timer 15, that was setup to pace its own DMA stream.  Now I can get tier 15 triggering and DMA transfering it I enable it via the end of event cllback for timer 5, but DMAing to CR1 of an diabled timer doesn’t seem to work.It’s a very complicated problem! // Arm one amplitude bank, started by a TIM5 countdown delay to trigger DMA write to enable a target timer with DMA streamHAL_StatusTypeDef ArmOneBank(uint32_t *pwm_values,

Device: STM32H523xxReference Manual: RM0481Description of Issue:We are observing an apparent discrepancy between the documented initialization behavior of the Epoch programming registers and the actual silicon behavior.According to RM0481 Table 90 (Option byte loading description), both FLASH_SECEPOCHR_PRG and FLASH_NSEPOCHR_PRG are specified to be loaded from option bytes during a system reset / option byte reload sequence. This implies that after a successful boot or reload cycle, the _PRG registers should mirror the current active values found in their respective _CUR registers (FLASH_SECEPOCHR_CUR and FLASH_NSEPOCHR_CUR).However, during live register readbacks in our firmware (running at HDPL1), both FLASH_SECEPOCHR_PRG and FLASH_NSEPOCHR_PRG consistently read back as 0x00000000, even when the corresponding _CUR registers contain non-zero, successfully committed epoch values.Per §7.11.21 and §7.11.22, both _CUR registers allow Secure/Non-Secure reads and are behaving exactly as exp

Hello I’m planning to try using the ToF sensor (VL53L5CX) on the B-CAMS-IMX (MB1854B) with OpenSTLinux on the STM32MP257F.Looking at the kernelconfig,> Device Drivers > Industrial I/O support > Proximity and distance sensorslists “STMicroelectronics VL53L0X ToF ranger sensor (I2C)”; can I use the VL53L5CX with this driver? Or would it be better to use this driver instead?Linux driver for VL53L5CX multi-zone sensor For now, before I set up a device driver,I’m planning to try accessing it via the I2C driver using Ultra Lite Driver (ULD) for VL53L5CX multi-zone sensor Best Regards,--okn

MCU: STM32MP215DAN3 (custom board, STM32MP2 series)STM32CubeMX versions tested: 6.17.0 and 6.18.1 — identical crash in bothSTM32Cube FW_MP2: V1.3.1Steps to reproduce:Open a working project where SDMMC1 is the boot device (A35 ROM + A35S(TF-A_BL2) runtime context checked) In SDMMC1 Mode and Configuration: uncheck A35 ROM and A35S(TF-A_BL2) In SDMMC2 Mode and Configuration: check A35 ROM and A35S(TF-A_BL2) (making SDMMC2/eMMC the new boot device instead of the SD card) Save project, click Generate CodeResult: Code generation crashes with the following exception, reproducible 100% of the time with this exact configuration: java.lang.NullPointerException: Cannot invoke "javax.swing.table.TableModel.getRowCount()" because "RifIPExtraTableModel" is null    at com.st.microxplorer.mcu.rif.RIFService.getExtraTableModel(RIFService.java:341)    at com.st.microxplorer.codegenerator.McuDataModel.getRIFInfo(McuDataModel.java:824)    at com.st.microxplorer.codegenerator.McuDataModel.initMcuData(McuDa

The old forum allowed this, but I can’t see it in the new one.Related: 

Board: custom STM32N657Z0H3Q (not a Discovery/Nucleo)Flash: Macronix MX25U12835F, 16 MB, Quad (x4), 1.8 V, no DQSTools: STM32CubeProgrammer 2.22.0 and 2.23.0, LinuxWe need to program the external XSPI NOR flash (FSBL + application) using only USB serial boot / DFU, with no ST-LINK connection.This is a product requirement, not a bring-up convenience. On our board, entering development boot requires BOOT1 = 1, and BOOT1 (PA6) is wired as DCMIPP_PIXCLK and actively driven by an on-board FPGA. We cannot reliably force that pin without contending with the FPGA driver. USB serial boot needs only BOOT0 = 1 and BOOT1 = 0, which is the FPGA-idle state, so it is the only strap combination that is safe on this hardware. We attempted to relocate BOOT1 via OTP19 dev_boot_port/dev_boot_pin, and that attempt left the board permanently inaccessible. That is a separate open thread with no resolution so far: https://community.st.com/stm32-mcus-products-25/stm32n657-after-programming-otp19-dev-boot-port-

It says one: But there’s two marked as ‘new’: 

I am trying to understand the readout protection functionality in the STM32G4 series. When I read the G4 series manual, I get the impression that level 1 protection will protect the flash, option bytes, CCM SRAM and RTC backup registers from JTAG / SWD readout – but curiously not the regular SRAM.Have I understood this correctly?Furthermore, I understand that level 2 will protect the entire chip – but that this is irreversible. So, if I do that to a chip, I can never again use that one for debugging. Not even after a full chip erase, which I’m not even certain that I can perform. As a developer, I see this as pretty much bricking the board.If I am correct that RDP level 1 will not protect the regular SRAM from readout via JTAG or SWD, are there other ways to protect it from JTAG / SRAM probing?

 Those badges are “Replies contributed: 1”, and “Solution Contributor: 1” I had a notification this morning of a reply by this user:but there is no such reply.I guess this is all “ghosts” of activity that’s been removed as spam?This forum does seem rather poor at handling spam: See also:I had to resort to an external search engine to find the user’s profile.

Hi there,I’m using STM32L052 for PWM generation with TIM2.TIM2->CR1 is initialized once at start of the program and never touched again during runtime:TIM2->CR1 = 0x00000081;Even though, in some random cases TIM2->CR1 switches back to 0. How can that happen? How can TIM2->CR1 accidentally switch back to 0? Is there a known issue? I really don’t know how to debug such an error. TIM2->CR1 is the only register that changes randomly.Thanks in advance for your help! 

HiSetup: LIS2DW12 in I2C mode, with CS and SA0 tied to VDD_IO and RES (pin 7) to GND. VDD and VDD_IO are always on. An ST25DV shares the bus. With the original 100 kΩ pull-ups we measured t_HIGH(SCL) = 3.2 µs, below the 4.0 µs minimum, and edges of about 2.2 µs.The firmware sets SOFT_RESET by read-modify-write on CTRL2 on every sleep cycle, then sets BDU by read-modify-write.Symptom: after some time the sensor stops acknowledging at any address. The ST25DV on the same bus still works. MCU reset and 9 SCL clocks + STOP do not help.Bus already fixed: we replaced the external pull-ups with 10 kΩ, as in Figure 4, and adjusted the I2C timing register. t_HIGH is now about 7 µs and f(SCL) is about 67 kHz, within Table 7.Questions:1. Apart from I2C_DISABLE = 1, what can make the sensor stop responding on I2C until power is removed? Could the previous out-of-spec timing have caused a wrong register write?2. Is a read-modify-write of CTRL2 right after SOFT_RESET safe? Is there a minimum wait tim

The old forum had a facility to report a User Profile; eg, an inappropriate avatar or username or for spamming.This was separate from reporting Posts.I don’t see that on the new forum ?  

Hello,I am using an STM32N6570-DK and I am seeing an issue when trying to start a TouchGFX application after programming the board.My setup is: STM32N6570-DK TouchGFX Designer 4.26.1 STM32CubeMX 6.18.1 STM32CubeIDE 2.2.0 STM32CubeProgrammer 2.23.0 ST-LINK firmware: V3J17M11 STM32 Debug+VCP I created a new project using TouchGFX Designer 4.26.1. The only additional component I added was a simple colored screen, just to have something visible when the application starts.I then generated the TouchGFX code from Designer and generated the project using STM32CubeMX 6.18.1 for STM32CubeIDE 2.2.0. The complete project builds successfully without any errors.To program the board, I do the following: Set BOOT0 = 0 Set BOOT1 = 1 Press the RESET button Use the LoadAll.bat script located in the project's Flash scripts folder, from the CubeIDE/Debug, to program the application The programming process completes successfully.After programming, I then: Set BOOT1 = 0 Press RESET However

Hello,We are currently implementing the STMicroelectronics PWD5T60 power stage in our SMT production and would like to ask for stencil design recommendations for this package (VFQFPN 12x12 with multiple exposed power pads). [st.com]We are currently experiencing significant solder voiding on the large exposed pads after reflow soldering.Our current process uses:Solder paste: KOKI S3X58-M650 Standard convection reflow processWe are planning to evaluate KOKI HF1200 as an alternative paste, but before starting trials we would be interested in ST's recommendations and experience with this package.Could you please advise:Recommended stencil thickness Aperture design for the exposed power pads Target paste coverage (%) Any specific PCB land pattern recommendations Typical voiding performance observed during qualification Available assembly guidelines or application notes for PWD5T60Has anyone worked with this device and successfully optimized the stencil design to reduce voiding?Any recommend

Hi,we are currently using STM32H745BIT6 208 Pin package, now this package is not recommended by ST for new designs, so we are changing to STM32H745II LQFP 176 pin package.is there a way to import the current project IOC file MCU to new MCU. how to do this. if I do again by creating new project it is a huge work. since we are in a production stage this change in new MCU will cause us several software related problem and it will consume again more time.please suggest how to import current project to new MCU Regards,srinath

Hi,I would like to share a solution that may help others using USBX Custom HID on the STM32H723.EnvironmentSTM32H723 STM32CubeMX 6.17 STM32CubeH7 V1.13.0 USBX + ThreadX USB_OTG_HS (Internal FS PHY) Custom HID 64-byte reports IN and OUTProblemThe device enumerated correctly and received HID SET_REPORT requests.A worker thread processed the received command and sent a response using: ux_device_class_hid_event_set(&hid_event); After the first IN report, the application appeared to hang.The CPU spent nearly all its time inside: OTG_HS_IRQHandler() and ThreadX tasks no longer received meaningful runtime.Debugging ResultsThe following registers were observed:DAINT     = 0x00000002DIEPTSIZ1 = 0x00080040DTXFSTS1  = 0x00000000 This indicated that EP1-IN had a pending 64-byte transfer and the Tx FIFO remained blocked.HAL_PCD_EP_Transmit() returned:HAL_OKbut the transfer never completed. Root CauseCubeMX generated no FIFO configuration for the USB OTG HS peripheral.The following functions wer

We are considering using a WB05KN as a BLE coprocessor in an STM32H573 design.  I found the section in your wiki describing paths for Bluetooth certification.  It says that no testing is required if a precertified module is used, or the recommendations and layout in AN5526 have been followed to the letter.Separately, all intentional radiators (in the US) must pass FCC testing, but if one uses a precertified wireless module and specified antenna, then the incorporating product can simply cite the certification of the wireless module.I want to clarify… are these two sets of testing (Bluetooth qualification as discussed in the ST Wiki, and FCC intentional radiator testing) two different sets of testing entirely?  That is, if we do a chip-down WB05KN design according to AN5526, would we still have to do FCC intentional radiator testing, even though we would not need to perform Bluetooth certification testing?If I’m understanding that correctly, is it then true that the only way to avoid FC

Hello,I am using NUCLEO-U5A5ZJ-Q evaluation board.I have configured ADC1 to do a single conversion and a software start.I want to measure ADC conversion time.My main test code looks like thiswhile(1){    HAL_ADC_Start_IT(&hadc1);            HAL_Delay(1);            HAL_ADC_Stop_IT(&hadc1);    adc_value = hadc1.Instance->DR;    }I have added a test pin for debugging. To check with oscilloscope.I set pin high inside HAL_ADC_Start_IT just before ADC enabled.And I reset pin inside interrupt procedure ADC1_2_IRQHandler.I have connected oscilloscope to ADC input pin directly to see sample begin. As ADC capacitor is connected to input and it has some chargeit is possible to see discharge curve on the screen.Here is the picture. Yellow shows time between start and end of sampling.Blue shows sampling begin (when capacitor is connected).Why there are two discharge curves?I have configured to do only one sample.Also the timing is wrong.I am using clock from external HSE.It is 16MHZ. Di

Hi,On STM32U575CGU3, calling MX_ADC1_Init() once increases the device current by about +200 µA. After that, even if I run HAL_ADC_DeInit(), reset ADC1, and disable VddA, the extra +200 µA current does not disappear.Here is the minimal code:cint main(void){ HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_GPDMA1_Init(); MX_ADC1_Init(); // <-- Base +200uA increase MX_OCTOSPI1_Init(); MX_SPI1_Init(); MX_USB_OTG_FS_PCD_Init(); MX_USART1_UART_Init(); MX_ICACHE_Init(); // ADC Disable HAL_ADC_DeInit(&hadc1); // <-- This does NOT reduce the +200uA __HAL_RCC_ADC1_FORCE_RESET(); __HAL_RCC_ADC1_RELEASE_RESET(); HAL_PWREx_DisableVddA(); while (1) { __NOP(); }}QuestionDoes ADC_Init enable an internal analog bias that cannot be fully disabled by ADC_DeInit, ADC reset, or VddA OFF? Is there any complete shutdown procedure to fully power down ADC/VREFBUF after initialization?Thanks.

I'm in debug mode in STM32CubeIDE.On the SFRs tab in the upper right corner, I want to enable UART4 and check the register status.But I only see UART-related items: LPUART/USART1/USART2/USART3.Why can't I find UART4?My MCU is an STM32C551RCT6.I'm very certain this IC has UART4

I’m making AOI program for STSAFA110DFSPL02 and would like the correct top marking because I couldn’t find it in the datasheet.The received part has SF3C B317 marked in the top side and need to confirm that is correct or not.

For TS972IQT, how to determine whether the DC  is 2013+ or 2023+ ?  thanks~