Question
PWD5T60 - Stencil design recommendation and voiding performance
Hello,
We are currently implementing the STMicroelectronics PWD5T60 power stage in our SMT production and would like to ask for stencil design recommendations for this package (VFQFPN 12x12 with multiple exposed power pads). [st.com]
We are currently experiencing significant solder voiding on the large exposed pads after reflow soldering.
Our current process uses:
- Solder paste: KOKI S3X58-M650
- Standard convection reflow process
We are planning to evaluate KOKI HF1200 as an alternative paste, but before starting trials we would be interested in ST's recommendations and experience with this package.
Could you please advise:
- Recommended stencil thickness
- Aperture design for the exposed power pads
- Target paste coverage (%)
- Any specific PCB land pattern recommendations
- Typical voiding performance observed during qualification
- Available assembly guidelines or application notes for PWD5T60
Has anyone worked with this device and successfully optimized the stencil design to reduce voiding?
Any recommendations would be greatly appreciated.
Thank you in advance.