Recently active topics

Hello,I am getting a hard fault while trying to integrate TouchGFX into a Zephyr application.The application is secure-only and the screen design is very simple: it contains a single screen with one box. When I debug the application, the hard fault occurs in the touchgfx::Application constructor (so I cannot debug), which is called indirectly through:FrontendHeap& heap = FrontendHeap::getInstance();I have already tried increasing the following Zephyr configuration values (CONFIG_MAIN_STACK_SIZE and CONFIG_HEAP_MEM_POOL_SIZE).CRC is enabled. DMA2D is disabled for now — the “Use DMA2D Accelerator” option is set to No in the X-CUBE-TOUCHGFX package, to keep the setup simple and eliminate one possible source of issues.The framebuffers are aligned and placed across AXISRAM3, AXISRAM4, and AXISRAM5The setup is as custom board with:MCU: STM32N65XXZephyr version: 4.4TouchGFX version: 4.26.1Zephyr SDK: 1.0.1I would appreciate any help, suggestions, or debugging directions.Thanks in advance.

Hello everyone,I’m using Nucleo STM32N6 for a project of mine, and I used template XIP to begin with.In template XIP, clock frequency of the XSPI2 is set to 50Mhz without any prescalers, and VDDIO3 is set to 1 (1.8V). That setup works fine for XIP up to 85Mhz clock frequency, but above that at BOOT (00) it fails as soon as it tries to jump to a application. I haven’t been able to resolve this problem. Is it setup, or something with EXT_MEM middleware?In MX25 datasheet it can be seen that frequency heavily depends on dummy cycles, and 86Mhz corresponds to 8 dummy cycles, but on 200Mhz it requires 20. In EXT_MEM setup there is a 8D8D8D case where i go into during setup and it sets object to 20 dummy cycles, but I’m not sure is it successful in actually forcing that setup. Any help would be welcome. 

Hello, There’s probably a solution, but I haven’t been able to fix it. Could you help me?In the circuits I’ve designed recently, the LSE crystal either doesn’t work at all or its operation is unstable. Generally, when debugging, it gets stuck at the SystemClock_Config(); section and won’t proceed.I’ve designed circuits using different MCUs and have encountered this problem across the board.  In my latest circuit design (4-layer FR-4), I used an STM32WBA54CGU6 MCU and, for the crystal, the ABS07-LR-32.768KHZ-6-1-T recommended in the AN2867 Application Note. I’m using an 8pF C0G 0402 package capacitor as the load capacitor. I also tried a 6.8pF capacitor, but it didn’t work at all. The 8pF capacitor is also unstable. I tried driving it in different modes (LOW, MEDIUM, MEDIUMHIGH, etc.), but it remains unstable. I didn’t adhere perfectly to the layout rules, but I haven’t experienced problems in previous circuits where I followed them even less strictly. I’m trying to keep as few signals

B-G473E-ZEST1SControl Discovery kitSTEVAL-LVLP01Power Discovery kitST offers a sensorless control solution featuring the ZeST (Zero Speed ​​Full Torque) algorithm, bundled with two Discovery kits: the B-G473E-ZEST1S Control Discovery kit and the STEVAL-LVLP01 Power Discovery kit. However, the power board has a relatively low output current (approximately 5 Arms). I would like to know if the ZeST algorithm can be implemented on a different power board that supports a higher output current.

Hi all,I am bringing up the Ethernet switch (ETHSW) on an STM32MP257F-DK, bare-metal on the Cortex-A35 (no OS), following RM0457 Rev 5.Ping works with the switch bypassed (ETH1 directly to the PHY), and ping also works under Linux with the switch enabled on the same board. In bare-metal switch mode, ARP works but ICMP never arrives.SETUP- ETH1 -> Port0 (internal, no PHY), PHY (RTL8211F, RGMII) on Port2, negotiated 100 Mbps full duplex- SYSCFG_ETHSWCR = 0x6   SYSCFG_ETH1CR = 0x12 - Init order:ETHSW reset -> clocks -> SYSCFG_ETHSWCR -> release reset -> pulse ETHSW_FES_GEN_CTRLR INIT_REQ (bit 15) -> then ETH1 clocks/reset/DMA- PORT0 UNDER MANAGEMENT,MII,100 MBPS- PORT2 UNDER NORMAL, MII,100 MPBS WHAT WORKS- Broadcast/multicast from the PC reach ETH1 (ETH1 MMC broadcast counter increments)- The board's ARP reply (unicast) leaves ETH1, crosses Port0 -> Port2 (Port0 RX_UNICAST=1, Port2 TX_UNICAST=1) [confirm in Wireshark that the PC actually receives it]- Dynamic MAC tab

I had trouble setting the PLL3N field in PLL3DIVR in an STM32H533.  The documentation says the field CANNOT be set if PLL 3 is enabled.  I spent a whole day running iterations, trying to turn PLL 3 off, reordering writes, etc.  What I FINALLY found is that the field CANNOT be set if PLL1 is enabled, i.e. the WRONG PLL.The following code fails: RCC->PLL1CFGR = 0x00030007 | ( XTalMHertz << 8 ); // PLL 1 Input = 1 MHz; HSE in; RCC->PLL1DIVR = 0x00000000 | ( SystemMHertz - 1 ); // DivN = VCO Output in MHz RCC->CR |= RCC_CR_PLL1ON; // Enable PLL 1 while(( RCC->CR & RCC_CR_PLL1RDY ) == 0 ) { } // Wait till PLL 1 is ready RCC->PLL3CFGR = 0x00070007 | ( XTalMHertz << 8 ); // PLL 3 Input = 1 MHz; HSE in; RCC->PLL3DIVR = 0x030306BF; // DivN = 192 (n=191); R/4, Q/4; P/4 RCC->CR |= RCC_CR_PLL3ON; // Enable PLL 3 while(( RCC->CR & RCC_CR_PLL3RDY ) == 0 ) { } // Wa

I am evaluating STiRoT + OEMuRoT on an STM32H5F5J-DK using the STM32CubeH5 v1.7.0 package by following the ST documentation:Security:OEMiRoT OEMuRoT for STM32H5 - stm32mcu How to start with STiRoT_OEMuRoT on STM32H573 - stm32mcu Getting started with STiRoT (ST immutable Root of Trust) for STM32H5 MCUs - Application noteThe board can be provisioned and the following currently work correctly:-  STiRoT starts successfully.-  OEMuRoT starts successfully.-  Secure and non-secure applications are authenticated and executed normally.-  Application updates (swap mode) through the OEMuRoT flow are functional.The next step is to confirm whether the OEMuRoT authentication and encryption keys can be updated after the board has already been provisioned, without reprovisioning the complete board. Test procedures as below:Generate new OEMuRoT keys Using STM32TrustedPackageCreator (TPC), a new set of OEMuRoT authentication/encryption keys were generated through ‘OEMuRoT_Config_Keys.xml’ Generate the O

UL have requested CDRH certificate for VL53L8CX. Can anyone help?

I'm working on a battery-powered sensor node using an STM32L4 series MCU. I need to wake from STOP2 mode on either of two GPIO interrupts (button press or external sensor trigger) and want to identify which one triggered the wake before running my main loop.What's the recommended way to configure and distinguish the wake source cleanly — checking EXTI pending register flags right after wake, or is there a better pattern people use for this?

I am currently working with the VL53L1X Time-of-Flight (ToF) distance sensor and am experiencing inaccurate and inconsistent distance measurements.The sensor is able to detect objects and provide distance readings, but the measured distance does not consistently match the actual physical distance. I have observed variations/errors in the distance readings even when the target position remains unchanged.Could you please help me identify the possible cause of this issue and suggest the recommended configuration or calibration procedure?I would appreciate your guidance regarding the following points:* Recommended initialization and configuration settings for the VL53L1X.* Recommended timing budget and ranging frequency settings.* Calibration procedure for accurate distance measurement.* Recommended offset and crosstalk calibration procedure.* Effect of target reflectance, ambient light, and target size on measurement accuracy.* Recommended sensor mounting and target conditions for reliabl

Hello, I am using VL53L9CX with adapted drivers for ESP32 / Arduino environment. I am able to read values and play with the settings but I am a bit worried with the precision I get. I run the sensor in precision mode, 4ms exposure time. My bench is indoor. Sensor facing the ground ( 1 m ish, wood) or the roof (1.6m ish, white ceiling). Resolution is 8 x 6 (Binning 12). I have radial to perpendicular conversion enabled so I am expecting to see all distances being equal +/- precision across the cells of the frame (excluding corner cells maybe). According to table 34: Precision for “ambient mode 24x20” profile from the sensor datasheet: (results are better for 24*20 then they are for 54*42, so I assume it is the same or better for 8*6 compared to 24*20)I am expecting less than 0.8 mm difference between the values but instead I get 50 mm - 100 mm or more of difference. So I was wondering, is there some specific settings to enable to achieve such precision / accuracy ? PCB is of my own (not

Hello ST, I wonder if the top marking of STS10P4LLF6 is indeed 10P4L.Based on the latest datasheet (Rev 5, issued in Jan 2021), the top marking code is 10P4L.However, we received STS10P4LLF6 with “10K4L” but the date code is 2447. Could you please explain how this could happen?Best regards,

Hi, i am using the TCPP03-M20 for the first time. This device is stand alone. i have the device setup for 5V, which is all that is required. there is no power to the device initially when connected to the USB-C port. CC1c and CC2c pins are at around 1.65V. i do not see any voltage on Vbus. have attached the schematic section for this circuit. .If i apply 3.3v to Vcc_Vconn VBUS is still 0V. Any help appreciated. Mark

hi I’m using the board named NUCLEO-N657X0-Q and I want to use feature of FDCANbut I couldn’t find pin map for that where is the pin number for FDCAN? Thanks

Hi,This is for STM32U5 and STM32H7 series MCUs.I was starting to use ThreadX because it looked like it was preferred over FreeRTOS. Now it looks like it is going the other way FreeRTOS is preferred over ThreadX ... or so I read/watched.I liked ThreadX with FileX because they seemed better integrated than FreeRTOS and say FATfs. But I don't have a lot of experience with RTOS in general. I've used a bit of FreeRTOS before but it looked like ThreadX was a better option for STM32U5 series MCU (in cubeMX).The video I watched and info on going back to FreeRTOS  with separate FileX (from STM) said that it was going to happen by the end of 2025. I prefer to stay with one RTOS, whichever is going to make my life easier but I also need a file system.We're at the end of 2025 so I wonder if this switch from ThreadX to FreeRTOS with separate FileX has already been implemented in the new STM32cubeIDE v 2.0? BTW I'm currently using STM32CubeIDE v1.19.0 with Windows 11.Comments/suggestions w

I designed a small PCB for LSM6DSV but I got no signal on SPI-MISO and got NACK on I2C-SDA.I have replaced several chips but all the chips have the same behaviour(no signal reply).I'm very sure the SPI and I2C pins are correctly connected to LSM6DSV.(1)Custom PCB designThis is the PCB design of my custom board. All the net label are connected to pads on board. Never mind "LSM6DSOTR" in the schematic. Actually I soldered LSM6DSV on board since LSM6DSV has the same chip package with LSM6DSO.VDDIO and VDD are 3.3V and this board shares the same ground with stm32.(2)SPI communication issueSPI_SCK and SPI_MOSI signal is correct but SPI_MISO has no signal.I configured STM32H743XIH6 SPI in STM32CubeMX like this. No NVIC, no DMA.I implemented the SPI polling read/write function for official ST LSM6DSV driver code. int32_t lsm6dsv_spi_read(void* handle, uint8_t reg, uint8_t *data, uint16_t len) { reg |= 0x80; LL_SPI_SetTransferSize(handle, len+1); LL_SPI_Enable(handle); LL_SPI_StartMas

In document PM0264, chapter 4, section 4.3.11, it is referring to System handler control and state register (SHCSR) of the System control block (SCB).However, Table 75 of that section is describing the fields of Configuration and control register (CCR). It seems the content of table 70 of CCR register and table 75 is somewhat similar, and the fields of SHCSR register is completely missing!Does anybody know if this is an issue with the document, or am I reading it wrong? I want to read more about SHCSR register but it’s nowhere to be found in this document.Table 70:Table 75: 

PROBLEM:When loading a program, with size filling an odd number of memory sectors, into flash memory the program only starts every other upload. I have a custom board with an STM32L4KBU. I am connecting to the stm32 with the STLINK-V3SET, over SWO. I am developing with the VSCode STM32CubeIDE extension pack, on linux mint.STM32CubeProgrammer version: 2.23.0Boot0 pin is pulled to GND through 10k, default boot option bytes When using the STM32_Programmer_CLI to upload code there is a bug where the FLASH_SR PEMPTY register is not cleared correctly. It appears that the flash loader resets the register by writing all 1s, but the PEMPTY bit is specifically write 1 to toggle. This actually seems to be an odd design choice as the rest of the bits are write 1 to clear, and the language in the RM0394 Reference Manual is quite inconsistent (section 3.7.5, bit 17). A correct reset is to set this register to itself.The FLASH_SR register seems to get this toggling for every sector written into flash

Hi, I'm having some issues with the STM32WB06 when trying to achieve low power consumption. I hope someone can help me solve these problems. Issue 1: After initializing the Bluetooth protocol stack and enabling automatic connection establishment, it causes the device to fail to enter the low power state (BLE wake-up has been disabled). Is this a normal phenomenon? If not, what are the solutions? Issue 2: Before entering the low power mode, disabling automatic connection establishment allows the device to enter the low power mode normally. However, after waking up, attempting to re-enable automatic connection establishment fails (aci_gap_start_procedure(GAP_AUTO_CONNECTION_ESTABLISHMENT_PROC, LE_1M_PHY_BIT, 0, 0)). What is the solution for this problem?   I look forward to your replies. Thank you very much!

I’ve got a working graphics system.  It does high level operations on a 32 bit virtual image of the display’s resolution.   The image is then translated to a 16 bit buffer image (RGB565 for an ILI9341 display).  That image is then transferred over SPI to the display.  The SPI drivers can be polled, interrupt driven, or DMA driven.  Software drivers are used for all of this, and work.Moving to a different processor (U575 from L562), ChromART is available.  It could be used for filling the virtual image, translating to the RGB565 image.  2D DMA can be used to transfer modified blocks to the display.Now the problem.The transfer works erratically in some cases.  Some data (and I’m using mostly saturated colors) doesn’t transfer well into RGB565 (say 100% blue), it may just end up with black.  Other times, the complete color palette is transferred properly.I’m investigating whether or not the repeated restart of the ChromART peripheral is a problem.  Mostly what happens is that the mode sho

I am struggling to get TouchGFX running on my custom board. The processor is the STM32H7A3RGT and I am driving a 320 pixel x 960 pixel LCD display. I have allocated a frame buffer in internal RAM and have LTDC producing PCLK, DE, VSYNC and HSYNC. I have configured my firmware using CubeMX to use FreeRTOS. I added a call to MX_TouchGFX_Process in my default task but it gets stuck on an assert. Specifically here:Call StackThe reason it gets stuck is because pxQueue->ixItemSize is not zero !ASSERT in xQueueSemaphoreTakeWhat am I missing ?Andy

Setup:MCU: STM32N657X0HXQ (Cortex-M55), STM32N6570-DK Boot architecture: FSBL (runs from internal RAM) → single secure Appli, no TrustZone split, executing XIP from external NOR (XSPI2, mapped at 0x70000000) PSRAM (XSPI1, APS256XXN-OBR-BG) also mapped via the same EXTMEM_Manager framework FW package: STM32Cube FW_N6 V1.4.1 Linker script places Appli's .isr_vector at 0x70100400 (0x400-byte header region reserved before it)What's confirmed working:FSBL boots, maps both PSRAM and NOR successfully via EXTMEM_MemoryMappedMode() NOR flash program/verify succeeds cleanly via ST-LINK GDB server I independently verified the vector table content with a raw GDB memory read (x/4xw 0x70100400), bypassing Eclipse's Memory view (which was misleadingly showing byte-reversed values — a display artifact, not real data): the actual words are correct — 0x34100000 (valid SP, matches linker's RAM origin) and 0x701066a5 (valid Reset_Handler address, correct Thumb bit set, inside the linked ROM range)The prob