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Stm32cubeAI studio output      -------------------------------------------------------------------                       STM32CubeProgrammer v2.23.0                        -------------------------------------------------------------------ST-LINK SN  : 0042001A3234510337333934ST-LINK FW  : V3J17M10Board       : NUCLEO-N657X0-QVoltage     : 3.30VSWD freq    : 8000 KHzConnect mode: Under ResetReset mode  : Hardware resetDevice ID   : 0x486Revision ID : Rev ZDevice name : STM32N6xxDevice type : MCUDevice CPU  : Cortex-M55BL Version  : --Opening and parsing file: NUCLEO-N657X0-Q_Appli.elfMemory Programming ...  File          : NUCLEO-N657X0-Q_Appli.elf  Size          : 2.60 MB   Address       : 0x34000000Erasing memory corresponding to segment 0:Erasing memory corresponding to segment 1:Erasing external memory sectors [16 57]Error: failed to erase memoryError: failed to erase memoryRun failed: Error: STM32CubeProgrammer exited with code 1 

Hello Team,I am integrating the VL53L8CX ToF sensor over SPI with an NXP i.MX8MP LPDDR4 EVK running Yocto Linux with kernel 6.18.20.I have created a Linux SPI driver based on the VL53L8CX communication requirements and added the sensor as an SPI device through the Device Tree.The SPI bus itself appears to be configured correctly, and the driver is being loaded. However, I am currently unable to successfully read the VL53L8CX device ID/registers from the sensor.Hardware:NXP i.MX8MP LPDDR4 EVK VL53L8CX sensor/module SPI interface SPI controller: ECSPI2 Chip Select: GPIO5_IO13 SPI device: spi1.0Device Tree configuration:&ecspi2 { #address-cells = <1>; #size-cells = <0>; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; vl53l8cx@0 { compatible = "st,stmvl53l8cx"; reg = <0>; spi-max-frequency = <1000000>; };};The driver is successfully loaded

iam using winbond SDRAM to connect in FMC pins to display image without rendering issue but it will not works. how to solve this any one can guide me 

From the documentation it sounds like the STM32WB vectors to the reset hander when it exits STANDBY and lower power modes, correct? 

Hi,Does anyone know if there is a list of the operating systems supported on the Cortex-A35 cores of the STM32MP257 ? Any information or pointers would be welcome.Thanks!

STM32MP257F-EV1: SPI3 Slave Mode — NSS Pin (PB1) Fails to Claim Despite Correct ConfigurationSummaryOn the STM32MP257F-EV1 evaluation board, configuring SPI3 in slave mode (spi-slave;) works correctly for the SCK, MOSI, and MISO signals, but the NSS (chip select) pin — PB1, using the documented-correct AF1 alternate function — silently fails to be claimed by the pin controller. No error or warning is logged anywhere. All three other SPI3 pins on the same bus, using the same AF1 value, claim successfully.HardwareBoard: STM32MP257F-EV1 (MB1936) MPU: STM32MP257FAI3 OpenSTLinux version: 5.0.15-openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18 Kernel: Linux 6.6.116-stm32mp-r3What we are trying to doConfigure SPI3 as an SPI slave (spi-slave; device tree property) so the STM32MP2 can receive data from an external SPI master over the same bus/pins already used for a sensor (previously configured as SPI master).Configuration usedCustom pinctrl group (added to stm32mp25-pinctrl.dtsi):spi3_slave_pins

Hello ST Support Team,We are working with the STM32MP257F-EV1 evaluation board and have identified a hardware/firmware-level restriction preventing us from using the SPI8 peripheral from the Linux (Cortex-A35) side, despite correct device tree configuration.Board: STM32MP257F-EV1OpenSTLinux version: 5.0.15-openstlinux-6.6-yocto-scarthgap-mpu-v26.02.18Kernel: Linux 6.6.116-stm32mp-r3The issue:When we enable the &spi8 node in our device tree (with correct pin configuration, matching the same pattern that successfully works for other SPI peripherals like SPI3), the driver never initializes at all. There is no error message, no warning, and no output anywhere in dmesg — the peripheral simply remains completely silent and unclaimed, as if the device tree node doesn't exist.What we've already investigated and ruled out:Device tree correctness — confirmed the node, pinctrl, and pin assignments are syntactically and semantically correct, following the identical working pattern used success

Subject: X-NUCLEO-CCA02M2 PDM-over-SPI capture issue on STM32MP257F-EV1 - discontinuous clocking suspectedHello ST Support Team,I'm working with an X-NUCLEO-CCA02M2 dual PDM microphone expansion board interfaced to an STM32MP257F-EV1 evaluation board, and I'm running into a data-quality issue I'd appreciate your guidance on.Setup:- X-NUCLEO-CCA02M2 board, using onboard microphone M2 (MIC_PDM34_OB), routed via SB10 solder bridge to CN10 pin 15- Connected to the STM32MP257F-EV1's SPI8 peripheral in Linux userspace via /dev/spidev, MISO on mikroBUS pin 5 (PZ1), clock supplied from SPI8's own SCK (mikroBUS pin 4, PZ2) to CN10 pin 29 (MIC_CLK_NUCLEO)- Power from CN6 pin 3 (3.3V), GND from CN6 pins 6/7- Capturing via repeated SPI read calls (spidev, bufsiz increased to 65536, Mode 0)Issue:Short, isolated SPI captures (around 2000 bytes at a time, with pauses between reads) show clearly responsive behavior - bit density in the captured stream increases noticeably when speaking near the microp

Hello Community :) We are using STM32N657 series MCU and flash MPN : S25FS512SDSBHV213, The flash supports two erase mode Hybrid (default) and Uniform erase. When we flash/overwrite a new binary it does not work properly, even the Full chip erase is enabled What we have to do for image to be working we have to go to erase external memory section and have to perform full chip erase and it takes roughly 5 mins to erase,​​​​​Without this it is not working, what we want, is there any option in the cubeprogrammer to erase the flash while/before programming ? other than this

I would like to know if STHV748QTR and STHV748SQ can be used as complete substitutes?

Hi ST team,I am currently evaluating the ST67W611M1 Wi-Fi module in NCP mode and am facing an issue where the module does not appear to boot correctly after firmware programming.Hardware SetupModule: ST67W611M1 Supply Voltage: 3.3V CHIP_EN: Driven High (3.3V) BOOT pin: Connected to GND (Normal Boot Mode) SPI_CS: Held High Firmware: T01 mission firmware (st67w611m_mission_t01_v2.0.106.bin) Programming Method: Standalone firmware download using USB-to-TTL UART Host MCU:  STEVAL STWINBX1 Development kit. (STM32U585)IssueAfter powering the module:CHIP_EN goes high correctly. BOOT remains low. Supply is stable at 3.3V. However, SPI_RDY never asserts high. I also do not see any activity on the SPI_RDY pin using an oscilloscope. Because SPI_RDY never goes high, the host cannot proceed with SPI communication.Verification Already PerformedSPI SignalsI have verified:SPI_CLK SPI_MOSI SPI_MISO SPI_CSSPI Configuration: Baud rate: 5 MBits/s and 2.5 MBits/s SPI Mode: 0 SPI Port: SPI2 on STM32U585 Rea

Where can I find STM32H5F5J-DK demonstration firmware full source code?

Hi ST,We have the SR6PX-EVBC8000P board with the chip SR6P6C8 and install the StellarStudio Version 9.1.0, we want to load a demo to the board,but we could not found the SDK for SR6P6, and the https://sr6.srxstudio.org/ site is also restrict, could you help to provide the SDK of SR6P6 or also add the account for me to enter the  https://sr6.srxstudio.org/ 

Hello ST Team,I am working on a design based on STM32MP257F and would like to better understand the Resource Isolation Framework (RIF) and resource ownership between the Dual Cortex-A35 and Cortex-M33 cores.I understand that peripherals can be assigned to different processing domains, but I am looking for a detailed reference that clearly defines:Which peripherals are typically operated by the Cortex-A35 and which by the Cortex-M33? Is there any official resource ownership matrix available for STM32MP257F? Can all GPIO banks  be assigned independently to either Cortex-A35 or Cortex-M33? Are there any peripherals that are exclusively accessible by one core and cannot be reassigned? How is ownership handled for the following peripherals? GPIO Ethernet MACs USB2.0 / USB3.0 FDCAN I2C SPI / OCTOSPI UART / USART SDMMC DDR Controller GPU / VPU / NPU LTDC / DSI / LVDS ADC / DAC Timers DMA / GPDMA Is there a document showing: Peripheral-to-core mapping Security attribution Trust

Hi,On STM32U575CGU3, I see a reproducible +200 µA increase in current after calling MX_ADC1_Init() once. Even after HAL_ADC_DeInit(), ADC reset, and disabling VddA, the additional current does not return to the original baseline.Here is the minimal code:cint main(void){ HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_GPDMA1_Init(); MX_ADC1_Init(); // +200uA increase MX_OCTOSPI1_Init(); MX_SPI1_Init(); MX_USB_OTG_FS_PCD_Init(); MX_USART1_UART_Init(); MX_ICACHE_Init(); // ADC Disable HAL_ADC_DeInit(&hadc1); __HAL_RCC_ADC1_FORCE_RESET(); __HAL_RCC_ADC1_RELEASE_RESET(); HAL_PWREx_DisableVddA(); while (1) { __NOP(); }}Questions Has anyone observed similar behavior on U5 devices (ADC bias or VREFBUF staying active after initialization)? Are there known conditions where ADC/VREFBUF analog blocks remain powered even after DeInit and VddA OFF? Any hints on additional steps required to fully shut down the analog domai

I’ve just recently started with the STM32 tool chain so some of these may be answered elsewhere. Platform is Debian.Some problems have been encountered due to the editor in STM Cube IDE doing unexpected things, one of which led to the loss of a considerable amount of code. In general the editor is a bit week compared with e.g. Sublime text   Your IDE designers should try that - when copying and pasting, the indentations are correct, with CUBE the text ends up over indented. I’m now editing in Sublime and then pasting the complete text into Cube.ST-link problem: This has a uart channel, on my STM32F4 Nucleo board, this is prewired to UART3 of the target, for printf type debugging. However, there is limited documentation on connecting a terminal to this UART (ST-Link PC end), and the listings in the /dev folder are :The debian terminal program “screen” will not connect to any of these. Also, on the redirection of printf on the target: most of the on-line resources for this topic indicate

I built up an application using STM32CubeMX and FreeRTOS but left BLE disabled. Now, I want to add that connectivity.I went back into CubeMX and turned on BLE with the HeartRate application. The only thing I changed were ASYNC_PRESALER and SYNC_PRESCALER so that the RTC time keeping would be correct.Now, whenever I allow appe_TI_Init() to execute, I get an IPCC_C1_RX_IT interrupt (VECTACTIVE = 0x3C) as soon as osKernelStart() is called. If I comment out the call to appe_TI_Init(), the rest of the code operates as before. Yes, I know that BLE is not running.What have I missed that causes the interrupt when it is not handled?Thanks

Board: STM32N6570-DK. STM32CubeIDE FSBL + Appli project, Appli XIP from external flash (EXTMEM_XIP_IMAGE_OFFSET = 0x100000, EXTMEM_HEADER_OFFSET = 0x400). Appli signed with STM32_SigningTool (-align) and flashed at 0x70100000.Symptom:- DEV boot (debugger loads and runs): the FSBL → Appli handoff works and the application runs normally.- Flash Boot (standalone): the FSBL prints "init done, calling BOOT_Application" and then nothing, every time. No fault handler output, no reset.Already checked:- JumpToApplication() disables SysTick, IRQs and both caches before setting VTOR/MSP (standard ST pattern). Under DEV boot, a valid SP/PC is read from the image.- Removed all snprintf/newlib use from the FSBL boot path, and a print after the VTOR switch; no change.- Offsets and signing match the extmem config.Key observation (SWD hot plug, STM32CubeProgrammer, no reset):- DEV boot: AP1 (Cortex-M55) reachable, core identified, memory readable.- Flash Boot while hung: AP1 completely unreachable (cor

I have a STM32F769I-DISCO and want to create some software and run it but i am having a problem.When i plug the board to the PC using a USB data cable, in the ST_LINK port (CN16) the board turns on, LD6 is on as well as LD5 while LD8 is blinking red. I can use the screen correctly but the problem is that my pc doesn’t seem to acknowledge the existence of the board. Nothing appears in the device manager and it makes no sound when i plug it in. Also the CN3 Jumper is placed on “stlk”. Is there something i am doing wrong?

I am doing a academic research project working with PLC for 24 VAC HVAC application, CENELEC Band B. We have previously used TI AFE031 with F28379D with single-carrier FSK modulation targeting ~38k baud, but ran into bandwidth/aliasing and noise immunity bottlenecks near 150 kHz due to analog filter. To solve this issue, we are looking into OFDM. Would it be possible to make EVLKSTCOMET10-1 work for this application? I am a student and have little experience with communications, so apologies for any inconsistencies. 

Hi,We are currently facing serious supply shortage issues with the MX66LM1G45GXDI00 flash memory.As a potential solution, I am considering modifying the design to use an external Quad-SPI flash memory instead of the current Octo-SPI flash.My understanding is that this change may require us to develop or modify the following:Quad-SPI flash drivers for the STM32U5G9 Flash initialization and memory-mapped access configuration Programming/firmware download utilities Production programming support Bootloader and/or application changes, if required TouchGFX/external-memory configuration, if applicableCould you please let us know whether suitable Quad-SPI flash drivers, BSP components, or programming utilities are already available that we could leverage, particularly for the STM32U5G9?I would also appreciate your comments on the key challenges and any guidelines or recommendations you may have for this development effort. In particular, I would like to understand the potential impact on memo

Dear all, I found an interesting effect using the CubeL4 and CubeMX generated files for a STM32L496 and use ADC1 and ADC3 (not simultaneously): What we do: We turn the ADCs on only when we sample data, otherwise they are turned off.  To turn the ADC off, we use HAL_ADC_DeInit which calls HAL_ADC_MspDeInit. Issue: HAL_ADC_MspInit and HAL_ADC_MspDeInit keep track of active ADCs through static variable HAL_RCC_ADC_CLK_ENABLED. Init increases the count, deinit decreases it. If, however, init and fails but we still call deinit the count wraps around to 0xFFFF FFFF - upon next init it wraps around to 0, but then the ADC clock is not turned on and initialization fails again. See the code snippets below: HAL_ADC_MspInit HAL_RCC_ADC_CLK_ENABLED++; if(HAL_RCC_ADC_CLK_ENABLED==1){ __HAL_RCC_ADC_CLK_ENABLE(); }   HAL_ADC_MspDeInit HAL_RCC_ADC_CLK_ENABLED--; if(HAL_RCC_ADC_CLK_ENABLED==0){ __HAL_RCC_ADC_CLK_DISABLE(); }   Suggestion: Check for underflow of&nbsp

Hello everyone,I used to work with U5 family microcontrollers. Recently I migrate to C5 families, and to MX2 UI.When I wanted to create interruptions for DMA UART events, normally I worked with RxEventCallback (classic). However, seems I´m not capable to find this same __weak function anywhere inside the hal_uart.c file. Am I missing something? I´m working with STM32C562R mcu, in CubeIDE 2.2Thank you everyone.

I already posted this topic but I got low engagement.XIP template works on 50Mhz clock for XSPI and it works good. If I bump up the XSPI frequency to 200Mhz without modifying anything else, it fail at BOOT_Application() in FSBL. XSPI setup should remain the same for both 50Mhz and 200Mhz if I’m not mistaken.Dummy cycles are set weirdly also. I print XSPI CLK, PRESCALER and dummy cycles setup before BOOT_Application(). CLK = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2); PRESCALER = (XSPI2->DCR2 & XSPI_DCR2_PRESCALER_Msk) >> XSPI_DCR2_PRESCALER_Pos; printf("FSBL CLK: %lu \r\n", CLK); printf("FSBL PRESCALER: %lu \r\n", PRESCALER); printf("FSBL Dummy: %lu \r\n", XSPI2->TCR); /* USER CODE END BSP */ /* Launch the application */ if (BOOT_OK != BOOT_Application()) { Error_Handler(); }XIP template example works (FSBL prints in FSBL, and Appli prints in APPLI)And when set at 200Mhz, it takes a while (~20s) before reaching BOOT_Application where

Hi there, can someone explain what the GP configuration of the STM32N6 is? I can only find information that the dedicated pinout is different (Datasheet Chap.7) but no more information whether this has any influence on the functionality. Is there any reason why the STM32N657H3QG is not available in “Tape and ring”  packaging?Thanks Mitja