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Other than reserving pins for the hardware-implemented debug interface (Fig. 1), what are the effects of the highlighted settings of the "Trace and Debug" category of CubeMX (Fig. 2)? Fig 1: Debug infrastructure (RM0433) Fig 2: CubeMX Trace and Debug...
In Figure 1 of the reference manual RM0433 for the STM32H743 (and STM32H742, STM32H753, STM32H750) no connection between cache and DTCM-RAM exists.  For all I know this is correct since the DTCM-RAM is not cachable.Table 7 on the other hand shows tha...
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