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graffiti · 2019-12-18

Hello,We are using STM32H743ZIT6 revision V.This is connected to an ethernet PHY device via RMII. The PHY outputs the 50MHz RMII REFCLK to drive the RMII on the STM.According to the following sources, the RMII TX data lines (TXD0 and TXD1) should be ...

graffiti · 2019-03-19

Hello,Using STM32H753VITx with STM32CubeMX 5.1.0, I would like to use SAI1-A as 'Master with MCO' and external synchro out, and SAI4-A as synchronous slave.SAI4-A doesn't show the synchronous slave option.Alternatively I could do it the other way rou...

graffiti · 2018-09-18

Hi,Checking the TRM for STM32H7 (RM0433) I see that in section 57.1 the following is listed as standards supported by the STM32H7:802.1-Qav-2009However I see no references to tx queues or traffic shaping etc.Does the STM32H7 support any 802.1-Qav-200...

graffiti · 2014-10-24

Posted on October 24, 2014 at 16:14Hi,I am using a STM32F437 and need to use the dual bank boot feature to perform live firmware updates. I have the boot0 pin tied to ground.According to the Reference Manual:In STM32F42xxx and STM32F43xxx devices, w...

graffiti · 2019-12-18

don't you just love those posts where you figure out a solution right after posting...Changing the drive strength on the TXD0, TXD1 and TX_EN signals to HIGH (they default to LOW from cubeMX) seems to push the timing into bounds, and the CRC errors o...

graffiti · 2019-03-20

Thanks Khouloud,Great to hear it's not a limitation of the smaller package/pinmux. We'll code around the issue for now and look forward to the next CubeMX release.Best regards, Kieran.

graffiti · 2014-10-27

Posted on October 27, 2014 at 20:42My understanding of NACK reception is that the last byte of a Master Receive is not acknowledged. I believe this is normal with i2c, and the master sending a STOP with NO acknowledge is how the slave knows not to s...

graffiti · 2014-10-27

Posted on October 27, 2014 at 15:36Hmm, unfortunately there is more.Waiting for the STOP bit to be cleared at that point (and also before CR1 register is modified in HAL_I2C_Master_Transmit) improves the situation, but hasn't solved it completely. I...

graffiti · 2014-10-27

Posted on October 27, 2014 at 15:06Wow, yes, that's exactly the problem!Adding this code just before the read-modify-write, triggers the trap after 20 seconds or so... //check for r-m-w problem if((I2C_CR1_STOP & hi2c->Instance->CR1) != (I2C_CR...

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STM32H7 RMII timing

SAI1-A and SAI4-A don't have synchronous slave option in LQFP100 package

STM32H7 supports 802.1Qav?

dual bank boot STM32F437 vs STM32F439

Re: STM32H7 RMII timing

Re: SAI1-A and SAI4-A don't have synchronous slave option in LQFP100 package

Re: STM32F4xx: I2C multiple slaves, very strange behavior

Re: STM32F4xx: I2C multiple slaves, very strange behavior

Re: STM32F4xx: I2C multiple slaves, very strange behavior