STM32H7 RMII timing

Hello,

We are using STM32H743ZIT6 revision V.

This is connected to an ethernet PHY device via RMII. The PHY outputs the 50MHz RMII REFCLK to drive the RMII on the STM.

According to the following sources, the RMII TX data lines (TXD0 and TXD1) should be sampled by the PHY on the rising edge of the REFCLK, and thus should transition around the falling edge:

• official RMII spec
• STM32H7 datasheets Table 112. Dynamics characteristics: Ethernet MAC signals for RMII
• the timing diagrams from the PHY

This is not what I am seeing. The STM seems to be transitioning the TX data lines on (or near) the rising edge of REFCLK. We are getting CRC errors detected at the PHY on the RMII interface side.

The trace attached shows a packet going out on the RMII. The scope resolution is 2ns, so it's possible the data lines do transition just before the clock edge, but according to the timing diagrams the transition should be at least 2ns before a clock rising edge.

Any idea how to solve this? I didn't manage to find a way to invert the clock at either end (PHY or STM). The PHY supports RGMII clock delay, but only on RGMII, not RMII.

Thanks, Kieran.