About tec683

tec683 · 2024-03-10

I'm trying to use the Azure FileX with the LevelX NOR OSPI driver to access a QSPI memory. I'm using an STM32H723 processor an OctoSPI peripheral to try to interface to a Winbond W25Q128JV QSPI NOR memory. Part of my struggle is there are examples o...

tec683 · 2024-03-10

I generated an Azure RTOS project with the FileX option with RAM disk simulator enabled. This was on a Nucleo-H723 board. I used STM32CubeMX 6.9.2-RC4. It was X-CUBE-AZRTOS-H7 v 3.2.0.The problem is the 'SRAM Disk Driver' option for the 'SRAM Disk ...

tec683 · 2024-01-23

I want to solicit the advice of those more experienced with the STM32 processors. I'm experienced in general with embedded software and peripherals such as SPI but only about 6 months in on the STM32 processors and only in the last few weeks have I b...

tec683 · 2023-12-24

This behavior seems like a bug.I’m using USBX CDC ACM on a H723 nucleo board. I’m trying to work with the blocking nature of the ux_device_class_cdc_acm_read. For my application, I would like to get data as soon as up to 256 characters are received b...

tec683 · 2023-12-12

I have spent over a week trying to get the USBX CDC ACM virtual com port to work on a STM32F7 family nucleo-144 board. I'm using an STM32F767 as a representative processor. I've tried multiple examples and approaches with no success. The device enum...

tec683 · 2024-03-18

Thanks for your response Tesla. I was able to get it to work.I will elaborate on how I approached it for those that might face a similar situation. The generated OSPI driver for LevelX NOR does support some customization in a header file but is hard...

tec683 · 2024-03-09

The adventure continues. I have become wise to the dysfunctional ways STM32CubeMX examples and code generation. The LevelX NOR Simulator Driver also uses a hard coded address that is the same as the default FileX SRAM disk sample driver. Using the s...

tec683 · 2024-03-09

Here is a safer solution that does not rely on a hard coded SRAM disk buffer address.In fx_stm32_sram_driver.h, add the code after /* USER CODE BEGIN EC *//* Exported constants --------------------------------------------------------*/ #define FX_SRA...

tec683 · 2024-03-09

I also encountered this error and can elaborate. It makes me question ST's regression testing and quality control as this is happening with generated code using default options.When using FileX with an SRAM disk, the SRAM disk defaults to being locat...

tec683 · 2024-01-24

To summarize, the variable size depends on the SPI word length. For 4 thru 8, a byte is expected. For 9 thru 16, a short (16b int) is expected, and for 17 thru 32, a 32b integer is expected. The SPI peripheral will use the defined number of bits w...

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Using LevelX NOR OSPI interface with QSPI memory

STM32CubeMX Azure FileX RAM Simulator Memory Corruption With Default Settings

Advice on SPI and DMA for 24bit data on STM32H723

USBX CDC ACM data read bug?

USBX CDC ACM on STM32F767 Nucleo board not working

Re: Using LevelX NOR OSPI interface with QSPI memory

Re: _fx_version_id[] is not set because FX_SYSTEM_INIT is not defined

Re: _fx_version_id[] is not set because FX_SYSTEM_INIT is not defined

Re: _fx_version_id[] is not set because FX_SYSTEM_INIT is not defined

Re: Advice on SPI and DMA for 24bit data on STM32H723