I've come across an MCU with UID {0x210044, 0x474b500e, 0x20383736} where banks are swapped despite the fact that this is not configured in the option bytes. #include <stm32u5xx.h>
#include <stm32u585xx.h>
#define FLASH_KEY1 0x4567012...
I configured SAI1 asBlockA: I2S async slave transmitterBockB: I2S sync slave receivermanaging the data transfers with GPDMA1. The slave transmitter works fine, I get the half transfer and transfer complete interrupts correctly. But for the slave rece...
I'm using the ADC1 and ADC4 with PLL as kernel clock (MSIS 24MHz pll'ed to 32768 Hz watch crystal / 2 x (11 + 2163/8192) / 24) = 5.632 MHz). The ADC1 in combination with the MDF "looses" every second sample. The ADC4 never gets ready. The errata shee...
On the STM32U5xx, ST decided to keep this interpretation of "match". It is present on other chips as well, see https://community.st.com/s/question/0D53W000004J0srSAC/stm32l0-lptim-generating-random-compare-match-interrupt-when-changing-compare-match-...
Ok - the init code turns everything back again: /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
{
/* Transmit */
cks...
If you would have looked into the init code, you would have noticed that it just shifts this value to the correct position in the peripheral register. Since it does not add any information, I left that as an exercise the reader.
@Younes LAHBIB I've described the setup as compact as possible, if you need more help to reproduce it, just write me. But I'm not going to invest more time, it took me far too long already to pin it and find a work around.
