I'm trying to use the LL interface to read 2 ADC channels (0 & 1) using DMA. They're configured pretty much as default, 12-bit samples into 16-bit memory variables. I don't see any errors. The transfer completes, as does the EOS. There's data in t...
What would be an efficient, low latency way to reflect the state of an input pin onto an output pin?Is there anything more automated than configuring the input pin as an EXTI, then in the interrupt handler, reading it and setting the state of the out...
I'm using both SPI1 and SPI2 on an STM32G071RBT Nucleo board, using STM32CubeIDE code generation and LL interface. Both SPIs are configured to use DMA for receive and transmit. SPI1 uses channels 2 & 3; SPI2 uses channels 4 & 5. The DMA transmit co...
Ah, that explains the behavior. The part expects to be actively driven only. You could try an external pull-up of 500 ohms or less. I think then you would see it rise up better. However, with a very strong pull-up, you might have trouble fully dri...
Hi TA,Are you sure the NSS pin is configured in the appropriate special function mode?Are you sure nothing else is driving that line?The fact that you are seeing a small change with the internal and external pull up suggests to me that at least the S...
Thanks Jan. The last link is the issue. I had just figured it out myself. Another annoyance with this bug is that any time you regenerate code, it puts the function calls back in the wrong order again!
Indeed checking the DMA CCR1 register immediately before the transfer, the transfer size, increment, etc. was all zeros!I stepped through the MX_ADC1_Init function above, which is tool generated code, automatically called from the main program before...
Thanks guys.ADC1_NUM_CHANNELS is defined as 2. (I thought the number is supposed to be the number of halfword transfers, not the number of bytes.)There is no change in the behavior when I change this to 4.The chip is the STM32G071RBT6.-- Bruce.
