About Aurelien Robert

Aurelien Robert · 2023-10-03

Hello,With CubeMX V6.8 (I did not check with latest update), there is a bug in the USART clock source selection, for chip STM32L451VETWhen selecting SYSCLK for USART2 or USART3 (did not check with UART4), in the function HAL_UART_MspInit() the clock ...

Aurelien Robert · 2023-08-31

Hello,I'm implementing QSPI on STM32L451 with a NOR FLASH memory (Micron MT25QL512ABB, 64Mbytes) for the first time, using DMA, for the moment it seems to work, but I'm surprised by the timings.CPU runs at 16MHz, QSPI clock speed is 8MHz. For this ex...

Aurelien Robert · 2019-09-11

Hello,I'm observing a stability issue on the internal voltage reference while using STOP mode.I'm using STM32L431, with : - VCC=1.9V - VCC_AN=2.8V - internal reference set at 2.5V with output buffer enabled in low impedance mode, decoupled with 100nF...

Aurelien Robert · 2018-10-22

Hello,I need to connect a STM32 to an ethernet peripheral that will send periodially an UDP frame on a specific port. I just have to listen on the port and handle the measure.Ethernet speaking, is there any problem or modification required to handle ...

Aurelien Robert · 2018-08-17

Hello,I'm developping a demonstrator with a shield I made to fit a Nucleo 144 - F207ZG board. My application uses ethernet link (TCP, UDP client and server) and FreeRTOS. Base project is generated from CubeMX and I work under Atollic True Studio. Thi...

Aurelien Robert · 2023-10-04

It is possible that the kernel clock being used is bigger the bus clock. So, it reads faster than refreshing the registers!Or maybe, if the AHB clock that runs the CPU and DMA is the same that the QSPI module (no prescaler), there are arbitrations th...

Aurelien Robert · 2023-10-04

Hello PeterI'm deeply sorry for my mistake, it's my only fault when I copied the init parameter from a project copy regenerated with cubemx to my previous project, I copied the same line for the three UART without thinking...Thank you and sorry again...

Aurelien Robert · 2023-10-03

Hello,I made new tests. If the QSPI clock (after prescaler) is equal or 2x lower than the AHB (CPU/DMA) clock, there are wait cycles between bursts, but if the QSPI clock is 4x lower (QSPI 16MHz and AHB 64MHz) there is no delay, all the data is read ...

Aurelien Robert · 2023-08-31

I guess you are using for the instruction commandCMD_READ_4B_QUADIO_INOUT0xEC. If so, according to the datasheet, 1Byte (instr)+ 4Bytes (address) + 2Bytes (NbData lg) which makes sense. Hello,Yes, this is the command I used. Where do you see 2 bytes ...

Aurelien Robert · 2018-10-15

Hello,Thank you very much for your answer, sorry for late reply, I had to work on another project and I'm just getting back to the initial project today :)I read your answer and I continued analysing the code from the F207_EVAL board that uses anothe...

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USART Clock selection bug / cubemx

Understanding QSPI memory transaction timings with DMA

[STM32L431] VREF unstable when using STOP mode and toggling on/off DAC

[LWIP] Direct connection between peripheral and STM32 ?

STM32/LwIP/FreeRTOS on Nucleo : how to handle ethernet link status change ?

Re: Understanding QSPI memory transaction timings with DMA

Re: USART Clock selection bug / cubemx

Re: Understanding QSPI memory transaction timings with DMA

Re: Understanding QSPI memory transaction timings with DMA

Re: STM32/LwIP/FreeRTOS on Nucleo : how to handle ethernet link status change ?