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ace0 · 2019-03-27

I have a system in which I have enabled IWDG in hardware (option bits). Now I would like to use preinstalled STM's bootloader to update the device, but I'm not sure if the IWDG will be started. In case the IWDG is started when Factory bootloader is b...

ace0 · 2017-02-01

Posted on February 01, 2017 at 12:25Hi,I'm struggling with the DMA stream reenabling. I'm using 6 DMA streams to transfer known amount of data from memory to periph. Streams are triggerd with two PWM timers in the master-slave mode (update and CC tr...

ace0 · 2016-11-24

Posted on November 24, 2016 at 22:06Hi, I'm using STM32F207 and I would like to trigger DMA transfer on the falling edge of the PWM (duty cycle). So, I have configured TIM1 in PWM mode and enabled CC1DE and CCDS bits. uint8_t outBuffer[16] = {0}; in...

ace0 · 2017-02-01

Posted on February 01, 2017 at 13:49Unfortunately I can't ignore it because I loose one transfer, as I've tried to emphasize in the previous post.Never the less than you for the help, your hint for the DIER helped me.Although DMA is in the direct mo...

ace0 · 2016-11-28

Posted on November 28, 2016 at 23:04excellent observation :) thanks, it works now... btw CCDS basically excludes triggering DMA transfer on CC and Update which means that one can't trigger two different streams with one timer? For example if I wou...

ace0 · 2016-11-28

Posted on November 28, 2016 at 19:17Sorry for the delay, I didn't have the board by my side for a few days... Here is the content of the TIM1 registers right before enabling the timer

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