stm32f2xx DMA re-enabling issue

[ace0]

Posted on February 01, 2017 at 12:25

Hi,

I'm struggling with the DMA stream reenabling. I'm using 6 DMA streams to transfer known amount of data from memory to periph. Streams are triggerd with two PWM timers in the master-slave mode (update and CC trigers). 

When transfer starts for the first time, everything works fine, but for each subsequent transfer I receive FIFO error interrupt flag, although DMA is configured in direct mode.

Pictures from the left side:

1. Before the first DMA transfer

2. After first (successful) transfer, all relevant DMA flags cleared and data counter set again

3. I

mmediately after DMA_Cmd(DMA2_StreamX, ENABLE); for every stream

4. Timers before (and after) enabling dma stream for the second transfer

Please notice that NDTR has been decremented for 1 (only 1) i

mmediately after enabling DMA stream although timers are disabled and all flags cleared, therefor there should be no triggering.

After enabling timers the rest 17 half-words are transferred correctly...

Can someone help me with this?

[waclawek.jan]

Posted on February 01, 2017 at 12:55

I receive FIFO error interrupt flag, although DMA is configured in direct mode

In direct mode, you can simply ignore it.

Otherwise, you would need to disable the trigger source (here: timer through respective DIER bit) and reenable it after reenabling the DMA. There is a thread here from maybe a year or two ago explaining this behaviour but I am not going to search for it now.

JW

[waclawek.jan]

Posted on February 01, 2017 at 14:20

https://community.st.com/0D50X00009XkaAtSAJ

 

[ace0]

Posted on February 01, 2017 at 13:49

Unfortunately I can't ignore it because I loose one transfer, as I've tried to emphasize in the previous post.

Never the less than you for the help, your hint for the DIER helped me.

Although DMA is in the direct mode, for some reason you must disable the trigger source and re-enable it after enabling the DMA

[waclawek.jan]

Posted on February 01, 2017 at 14:15

The reason is that DMA is level-triggered, and the trigger latch to catch the 'volatile' TIM events is not part of DMA but part of TIM.

Before I learned the trick with DIER, I worked around the same problem by forcing a trigger through respective bit in TIMx_EGR and then ignoring the result of first DMA transfer. This won't work well with M->P transfers I admit, I had the other direction.

JW