STM8 EXTI Clear Interrupt Flag

jamesfowkes · ‎2011-03-06

Posted on March 06, 2011 at 23:34

#interrupt #gpio #exti

jeff239955_stm1_st · ‎2011-05-17

Posted on May 17, 2011 at 15:12

Hi

I have a similar question. I am using an STM8S105.

My question is when does the STM8 uC clear the EXTI interrupt source? Most other peripherals have an explicit status bit that has to be explicitly cleared by the interrupt service routine(ISR). For edge sensitive Dig In interrupts I do not have to do anything and the interrupt source is cleared automatically by the uC.

My specific interest is in what happens when I enable two bits on a dig port to be edge-sensitive interrupts, and both edges occur within a few micro seconds of each other so that the first edge causes the micro to respond to the interrupt and the second edge/interrupt occurs during the ISR before it has returned. Is the second interrupt internally latched and generates a second call to the ISR immediately the first one ends, or is there a time window where the second edge/interrupt is ignored and is lost unless my ISR explicitly checks for it?

Thanks

jamesfowkes · ‎2011-05-17

Posted on May 17, 2011 at 15:12

Hi,

I'm using the STM8S (specifically the STM8S105C6).

James

lowpowermcu · ‎2011-05-17

Posted on May 17, 2011 at 15:12

Hi james,

Which STM8 deice are you using STM8S or STM8L ?

spiovan9 · ‎2011-10-06

Posted on October 06, 2011 at 23:17

Hi James,

did you eventually got a solution about the question?

I came across the same problem in an application which requires to read an encoder potentiometer which ha 2 channels 90° degree shifted each other.

Thank you

Stefano

Viktor POHORELY · ‎2011-10-11

Posted on October 11, 2011 at 15:04

For STM8S/A devices, there is no status flag to be cleared.

For STM8L devices, there is a status flag to be cleared.

In both cases, if your application timing does not allow to check status of the external pin in the interrupt, I could only recommend to use different ISR for each separate event.