Entering Halt mode with the IWDG enabled causes reset for STM8s003F3P6 Chip

[bhoeneveld]

Posted on October 21, 2013 at 03:28

I've checked the Option Bytes and the OPT3 byte is zero so the WDG_HALT bit is 0 which means that the MCU should enter Halt Mode without causing a reset when the watchdog is enabled.

However a  HALT or WFI generates a reset. I refresh the watchdog counter prior to the halt instruction and it still generates a reset.  If I do not set up IWDG then no reset is generated and the program continues correctly when it comes out of halt by an interrupt. I have set and reset the option byte for WDG_HALT  but it always generates a reset when the IWDG is enabled by software and halt is entered.  What should I set up to overcome this?  Is this a known problem with the chip? #stm8s-halt-iwdg

[alex23]

Posted on November 29, 2013 at 10:22

Have same problem with STM8L152K4

[moreno]

Posted on February 10, 2014 at 16:37

Hello,

maybe you're confusing IWDG with WWDG. In STM8S devices only WWDG can be ''suspended'' during low power mode, indeed there's WWDG_HALT bit in OPT3 byte indeed; IWDG can't, and it remains active even in low power mode. Your application must wake up periodically at least to feed the IWDG (Active halt mode), then it can go to sleep again. STM8L devices are different. They can suspend IWDG via Option Byte programming. Regards.