Control the initial level while using the Timer output compare mode

jjyeh1976 · ‎2009-10-02

Posted on October 02, 2009 at 09:13

jjyeh1976 · ‎2011-05-17

Posted on May 17, 2011 at 15:04

Hi,

I'm using the Timer 3 in output compare mode with toggles, each time the

interrupt occurred, I have to change the next match value (TIMx->CCRn).

My question is: is it possible to set the initial state in a known level?

I'vd try to use GPIOx->ODR, but this seems not work.

mozra27 · ‎2011-05-17

Posted on May 17, 2011 at 15:04

Hi,

You can configure the mode PWM mode1 or PWM mode2 in the TIMx_CCMR1 register and then select the polarity (CC1P bit) in the TIMx_CCER1 Capture/compare enable register 1.

regards

mozra